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1. 发明授权

US3743863A Transistorized electronic circuit employing resistorless bias network 失效
标题翻译：采用无阻抗偏移网络的电子绕线电路
公开(公告)号：US3743863A
公开(公告)日：1973-07-03
申请号：US3743863D
申请日：1971-11-03
申请人： MOTOROLA INC
发明人： HILBERT F , SEYMOUR A
IPC分类号： H03F3/191 , H03K17/00
CPC分类号： H03F3/191 , H03F2203/45162 , H03F2203/45198 , H03F2203/45208 , H03F2203/45498 , H03F2203/45606 , H03F2203/45612 , H03F2203/45704
摘要： Transistorized differential circuits include a biasing system that substantially reduces the need for resistors in the base circuits of the transistors being biased. An inductor coupled between the base of one of the transistors and a power supply forward biases the base-emitter junction of the transistor, and the other base is coupled to the same point of the power supply to bias the transistor so that the voltages at the bases of the transistors are substantially equal to each other, and are at substantially the voltage of the power supply to which the inductor is connected. This technique is applicable to balanced or unbalanced differential transistor circuits, and may be employed in amplifiers, mixers, limiters, multipliers and oscillators and in other small signal applications.
摘要翻译：晶体管化差分电路包括偏置系统，其基本上减少了被偏置的晶体管的基极中的电阻器的需要。耦合在晶体管之一的基极之间的电感器和电源向前偏置晶体管的基极 - 发射极结，而另一个基极耦合到电源的相同点以偏置晶体管，使得在晶体管的基极基本上彼此相等，并且基本上是电感器连接到的电源的电压。该技术适用于平衡或不平衡差动晶体管电路，可用于放大器，混频器，限幅器，乘法器和振荡器以及其他小信号应用中。

2. 发明授权

US09246484B2 Apparatus and methods for input bias current reduction 有权
标题翻译：输入偏置电流降低的装置和方法
公开(公告)号：US09246484B2
公开(公告)日：2016-01-26
申请号：US14201234
申请日：2014-03-07
申请人： Analog Devices, Inc.
发明人： Yoshinori Kusuda
IPC分类号： G05F1/10 , H03K17/16 , H03M1/66
CPC分类号： H03F1/0205 , H03F3/387 , H03F3/45179 , H03F3/45183 , H03F3/45556 , H03F2203/45044 , H03F2203/45454 , H03F2203/45466 , H03F2203/45544 , H03F2203/45562 , H03F2203/45604 , H03F2203/45606 , H03F2203/45702 , H03K17/162 , H03M1/66
摘要： Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.
摘要翻译：本文提供了用于减小电子电路的输入偏置电流的装置和方法。在某些实施方式中，电子电路包括第一输入端，第二输入端，输入电路以及包括至少第一输入开关和第二输入开关的多个输入开关。第一输入开关电连接在第一输入端和输入电路的第一输入端之间，第二输入开关电连接在第二输入端和输入电路的第二输入端之间，第一和第二输入开关可以使用时钟信号打开和关闭。电子电路还包括电荷补偿电路，用于在时钟信号转变期间补偿通过第一和第二输入开关的电荷注入。

3. 发明授权

US09735736B2 Apparatus and methods for reducing input bias current of an electronic circuit 有权
公开(公告)号：US09735736B2
公开(公告)日：2017-08-15
申请号：US14993969
申请日：2016-01-12
申请人： ANALOG DEVICES, INC.
发明人： Yoshinori Kusuda
IPC分类号： H03F1/02 , H03K17/16 , H03M1/66 , H03F3/45 , H03F3/387
CPC分类号： H03F1/0205 , H03F3/387 , H03F3/45179 , H03F3/45183 , H03F3/45556 , H03F2203/45044 , H03F2203/45454 , H03F2203/45466 , H03F2203/45544 , H03F2203/45562 , H03F2203/45604 , H03F2203/45606 , H03F2203/45702 , H03K17/162 , H03M1/66
摘要： Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.

4. 发明申请

US20140097907A1 MICRO CMOS POWER AMPLIFIER 审中-公开
标题翻译： MICRO CMOS功率放大器
公开(公告)号：US20140097907A1
公开(公告)日：2014-04-10
申请号：US13656899
申请日：2012-10-22
申请人： Sung Man YOON , Jong Jin PARK
发明人： Sung Man YOON , Jong Jin PARK
IPC分类号： H03F3/213
CPC分类号： H03F3/213 , H01L23/5225 , H01L23/5227 , H01L23/66 , H01L24/06 , H01L24/48 , H01L24/49 , H01L28/10 , H01L28/40 , H01L2223/6611 , H01L2223/6655 , H01L2224/04042 , H01L2224/05554 , H01L2224/06165 , H01L2224/48227 , H01L2224/49175 , H01L2224/49177 , H01L2924/00014 , H01L2924/19041 , H01L2924/19042 , H01L2924/19051 , H01L2924/19105 , H01L2924/3011 , H01L2924/30111 , H03F3/195 , H03F3/45188 , H03F2200/534 , H03F2200/541 , H03F2203/45464 , H03F2203/45538 , H03F2203/45594 , H03F2203/45606 , H03F2203/45611 , H03F2203/45621 , H03F2203/45641 , H03F2203/45704 , H03F2203/45712 , H03F2203/45731 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a micro CMOS power amplifier, in which an output transformer is configured as a substrate of a multilayer structure, and an amplifier circuit module is stacked on the output transformer. The micro CMOS power amplifier includes: an amplifier circuit module chip configured by modularizing circuits for amplifying power as a module; and an output transformer for outputting output of the amplifier circuit module chip to outside through a transformer circuit, in which the output transformer is implemented on a multilayer substrate, and the amplifier circuit module chip and the output transformer are configured as a stack.According to the micro CMOS power amplifier of the present invention described above, an output transformer occupying a large space in a conventional power amplifier is configured as a multilayer substrate, and thus the chip size can be reduced within 50% without decreasing output power of the power amplifier.
摘要翻译：微型CMOS功率放大器技术领域本发明涉及一种微型CMOS功率放大器，其中输出变压器被配置为多层结构的衬底，并且放大器电路模块堆叠在输出变压器上。微型CMOS功率放大器包括：放大器电路模块芯片，通过模块化电路来放大功率作为模块; 以及输出变压器，其通过变压器电路将放大电路模块芯片的输出输出到外部，其中输出变压器实现在多层基板上，并且放大器电路模块芯片和输出变压器被配置为堆叠。根据上述本发明的微型CMOS功率放大器，在以往的功率放大器中占据较大空间的输出变压器构成为多层基板，因此能够将芯片尺寸减小到50％以内，而不会降低输出功率功率放大器。

5. 发明授权

US07400203B2 Circuit with Q-enhancement cell having feedback loop 有权
公开(公告)号：US07400203B2
公开(公告)日：2008-07-15
申请号：US11590452
申请日：2006-10-31
申请人： Adedayo Ojo , Arya Behzad
发明人： Adedayo Ojo , Arya Behzad
IPC分类号： H03F3/04
CPC分类号： H03F3/45188 , H03F1/42 , H03F1/56 , H03F3/191 , H03F2200/451 , H03F2200/465 , H03F2200/78 , H03F2203/45521 , H03F2203/45606 , H03F2203/45626 , H03H11/1213 , H03H11/1291
摘要： According to an example embodiment, an amplitude feedback loop may include an RF amplifier, a detector, a comparator, and a Q-enhancement cell. In an example embodiment, the RF amplifier has an output signal, and the detector has an input coupled to the output signal of the RF amplifier and is configured to detect a level of the output signal of the RF amplifier. The comparator circuit may receive as inputs a reference voltage and the output of the detector. Also, the comparator circuit is configured to output a control signal based on a difference between the reference voltage and the output signal of the power detector. The Q-enhancement cell may be coupled to the RF amplifier and have an input coupled to an output of the comparator circuit. A bias current of the Q-enhancement cell may be adjusted based on the control signal output by the comparator circuit.

6. 发明授权

US08018288B2 High-linearity low noise amplifier 有权
标题翻译：高线性低噪声放大器
公开(公告)号：US08018288B2
公开(公告)日：2011-09-13
申请号：US12422430
申请日：2009-04-13
申请人： Jon S. Duster , Stewart S. Taylor
发明人： Jon S. Duster , Stewart S. Taylor
IPC分类号： H03F3/04
CPC分类号： H03F3/195 , H03F1/0255 , H03F1/0261 , H03F1/223 , H03F1/565 , H03F3/45179 , H03F2200/213 , H03F2200/216 , H03F2200/222 , H03F2200/225 , H03F2200/241 , H03F2200/243 , H03F2200/294 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/429 , H03F2200/61 , H03F2203/45352 , H03F2203/45544 , H03F2203/45548 , H03F2203/45554 , H03F2203/45606 , H03F2203/45608 , H03F2203/45631 , H03F2203/45638 , H03F2203/45704 , H03F2203/45714
摘要： Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion.
摘要翻译：这里通常描述高线性低噪声放大器（LNA）的实施例。可以描述和要求保护其他实施例。在一些实施例中，RF输入信号可以用共源共栅放大器放大。共源共栅放大器可以包括集成陷波滤波器以衰减不需要的信号。当存在阻塞器时，共源共栅放大器可以从大电源工作，以避免其输出端的电压摆幅压缩。共源共栅放大器可以被偏置并被设计为在AB类模式下操作以产生线性输出电流，以避免电流压缩或过大的电流膨胀。

7. 发明申请

US20100259331A1 HIGH-LINEARITY LOW NOISE AMPLIFIER 有权
标题翻译：高线性低噪声放大器
公开(公告)号：US20100259331A1
公开(公告)日：2010-10-14
申请号：US12422430
申请日：2009-04-13
申请人： Jon S. Duster , Stewart S. Taylor
发明人： Jon S. Duster , Stewart S. Taylor
IPC分类号： H03F3/191
CPC分类号： H03F3/195 , H03F1/0255 , H03F1/0261 , H03F1/223 , H03F1/565 , H03F3/45179 , H03F2200/213 , H03F2200/216 , H03F2200/222 , H03F2200/225 , H03F2200/241 , H03F2200/243 , H03F2200/294 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/429 , H03F2200/61 , H03F2203/45352 , H03F2203/45544 , H03F2203/45548 , H03F2203/45554 , H03F2203/45606 , H03F2203/45608 , H03F2203/45631 , H03F2203/45638 , H03F2203/45704 , H03F2203/45714
摘要： Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion.
摘要翻译：这里通常描述高线性低噪声放大器（LNA）的实施例。可以描述和要求保护其他实施例。在一些实施例中，RF输入信号可以用共源共栅放大器放大。共源共栅放大器可以包括集成陷波滤波器以衰减不需要的信号。当存在阻塞器时，共源共栅放大器可以从大电源工作，以避免其输出端的电压摆幅压缩。共源共栅放大器可以被偏置并被设计为在AB类模式下操作以产生线性输出电流，以避免电流压缩或过大的电流膨胀。

8. 发明授权

US07378907B2 Selective differential low-noise amplifier 失效
标题翻译：选择差分低噪声放大器
公开(公告)号：US07378907B2
公开(公告)日：2008-05-27
申请号：US11519789
申请日：2006-09-13
申请人： Jérémie Chabloz
发明人： Jérémie Chabloz
IPC分类号： H03F3/45
CPC分类号： H03F3/45201 , H03F1/26 , H03F1/565 , H03F3/193 , H03F2200/294 , H03F2200/372 , H03F2200/451 , H03F2203/45606 , H03F2203/45608 , H03F2203/45704
摘要： A selective differential low-noise amplifier includes a pair of transistors, each transistor of the pair being connected by its source to a current source and by its gate and/or its source to a differential voltage source, a coupling circuit between the gate of each transistor and the source of the other transistor of the pair, and, for each transistor of the pair, at least one series resonance and parallel resonance resonator connected in series between the source and/or the gate of the transistor and the differential voltage source.
摘要翻译：选择性差分低噪声放大器包括一对晶体管，该对的每个晶体管由其源极连接到电流源，并且其栅极和/或其源极连接到差分电压源，每个晶体管的栅极之间的耦合电路晶体管和该对的另一个晶体管的源极，并且对于该对中的每个晶体管，串联连接在晶体管的源极和/或栅极与差分电压源之间的至少一个串联谐振和并联谐振谐振器。

9. 发明申请

US20160126898A1 APPARATUS AND METHODS FOR REDUCING INPUT BIAS CURRENT OF AN ELECTRONIC CIRCUIT 有权
标题翻译：用于减少电子电路的输入偏置电流的装置和方法
公开(公告)号：US20160126898A1
公开(公告)日：2016-05-05
申请号：US14993969
申请日：2016-01-12
申请人： ANALOG DEVICES, INC.
发明人： Yoshinori Kusuda
IPC分类号： H03F1/02 , H03F3/45
CPC分类号： H03F1/0205 , H03F3/387 , H03F3/45179 , H03F3/45183 , H03F3/45556 , H03F2203/45044 , H03F2203/45454 , H03F2203/45466 , H03F2203/45544 , H03F2203/45562 , H03F2203/45604 , H03F2203/45606 , H03F2203/45702 , H03K17/162 , H03M1/66
摘要： Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.
摘要翻译：本文提供了用于减小电子电路的输入偏置电流的装置和方法。在某些实施方式中，电子电路包括第一输入端，第二输入端，输入电路以及包括至少第一输入开关和第二输入开关的多个输入开关。第一输入开关电连接在第一输入端和输入电路的第一输入端之间，第二输入开关电连接在第二输入端和输入电路的第二输入端之间，第一和第二输入开关可以使用时钟信号打开和关闭。电子电路还包括电荷补偿电路，用于在时钟信号转变期间补偿通过第一和第二输入开关的电荷注入。

10. 发明申请

US20150256169A1 APPARATUS AND METHODS FOR INPUT BIAS CURRENT REDUCTION 有权
标题翻译：输入偏置电流减少的装置和方法
公开(公告)号：US20150256169A1
公开(公告)日：2015-09-10
申请号：US14201234
申请日：2014-03-07
申请人： Analog Devices, Inc.
发明人： Yoshinori Kusuda
IPC分类号： H03K17/16 , H03M1/66
CPC分类号： H03F1/0205 , H03F3/387 , H03F3/45179 , H03F3/45183 , H03F3/45556 , H03F2203/45044 , H03F2203/45454 , H03F2203/45466 , H03F2203/45544 , H03F2203/45562 , H03F2203/45604 , H03F2203/45606 , H03F2203/45702 , H03K17/162 , H03M1/66
摘要： Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.
摘要翻译：本文提供了用于减小电子电路的输入偏置电流的装置和方法。在某些实施方式中，电子电路包括第一输入端，第二输入端，输入电路以及包括至少第一输入开关和第二输入开关的多个输入开关。第一输入开关电连接在第一输入端和输入电路的第一输入端之间，第二输入开关电连接在第二输入端和输入电路的第二输入端之间，第一和第二输入开关可以使用时钟信号打开和关闭。电子电路还包括电荷补偿电路，用于在时钟信号转变期间补偿通过第一和第二输入开关的电荷注入。

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