专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180205351A1 Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion 审中-公开
公开(公告)号：US20180205351A1
公开(公告)日：2018-07-19
申请号：US15916873
申请日：2018-03-09
申请人： DOCKON AG
发明人： Patrick Antoine Rada , Forrest James Brown , Alexandre Dupuy
IPC分类号： H03F3/193 , H03F3/195 , H04B1/22 , H03F3/72 , H03F1/56 , H03F1/38 , H03L7/06
CPC分类号： H03F3/193 , H03F1/38 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/129 , H03F2200/147 , H03F2200/222 , H03F2200/237 , H03F2200/241 , H03F2200/243 , H03F2200/246 , H03F2200/261 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/309 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/402 , H03F2200/438 , H03F2200/451 , H03F2200/462 , H03L7/06 , H04B1/22
摘要： An amplifying system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The amplifying system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.

2. 发明授权

US09973149B2 Source switched split LNA 有权
公开(公告)号：US09973149B2
公开(公告)日：2018-05-15
申请号：US15342016
申请日：2016-11-02
申请人： pSemi Corporation
发明人： Emre Ayranci , Miles Sanner
IPC分类号： H03F1/14 , H03F1/02 , H03F3/193 , H03F1/56
CPC分类号： H03F1/0277 , H03F1/086 , H03F1/565 , H03F3/193 , H03F3/195 , H03F3/72 , H03F2200/111 , H03F2200/18 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/252 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/321 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/411 , H03F2200/42 , H03F2200/429 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03F2203/7206 , H03F2203/7209 , H03F2203/7233
摘要： A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

3. 发明申请

US20180083578A1 Cascode Amplifier Bias Circuits 审中-公开
公开(公告)号：US20180083578A1
公开(公告)日：2018-03-22
申请号：US15268229
申请日：2016-09-16
申请人： Peregrine Semiconductor Corporation
发明人： Jonathan Klaren , Poojan Wagh , David Kovac , Eric S. Shapiro , Neil Calanca , Dan William Nobbe , Christopher Murphy , Robert Mark Englekirk , Emre Ayranci , Keith Bargroff , Tero Tapio Ranta
IPC分类号： H03F1/22 , H03F1/30 , H03F1/56 , H03F3/193
CPC分类号： H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

4. 发明申请

US20180054222A1 DIGITAL VARIABLE CAPACITANCE CIRCUIT, RESONANT CIRCUIT, AMPLIFICATION CIRCUIT, AND TRANSMITTER 审中-公开
公开(公告)号：US20180054222A1
公开(公告)日：2018-02-22
申请号：US15797618
申请日：2017-10-30
申请人： Renesas Electronics Corporation
发明人： Masakazu MIZOKAMI
IPC分类号： H04B1/04 , H03F3/24 , H03F3/19 , H03H11/48 , H03H19/00 , H03H11/32
CPC分类号： H04B1/04 , H03F3/19 , H03F3/245 , H03F2200/06 , H03F2200/09 , H03F2200/237 , H03F2200/243 , H03F2200/294 , H03F2200/399 , H03F2200/451 , H03H11/32 , H03H11/481 , H03H19/006 , H04B1/0475
摘要： A radio frequency integrated circuit includes an amplification circuit for outputting a radio frequency signal to an antenna, a balun including a first terminal, a second terminal, a third terminal, and a fourth terminal, and a variable capacitance circuit including a fifth terminal and a sixth terminal. The first terminal and the second terminal of the balun receive output signals of the amplification circuit. The third terminal and the fourth terminal of the balun are connected to the fifth terminal and the sixth terminal of the variable capacitance circuit, respectively, and the fifth terminal is connected to a radio frequency output terminal. The variable capacitance circuit includes a plurality of capacity cells that are connected in parallel between two output terminals.

5. 发明授权

US08000668B2 Transmit/receive circuit with PIN diodes 有权
标题翻译：带PIN二极管的发送/接收电路
公开(公告)号：US08000668B2
公开(公告)日：2011-08-16
申请号：US11823042
申请日：2007-06-26
申请人： Mihail Boguslavskij , Peter Nikles , Jürgen Reithinger , Ulrich Schätzle
发明人： Mihail Boguslavskij , Peter Nikles , Jürgen Reithinger , Ulrich Schätzle
IPC分类号： H04B1/16
CPC分类号： H03F1/52 , H03F3/191 , H03F2200/216 , H03F2200/243 , H03F2200/444 , H03F2200/451
摘要： Structurally simple transmit/receive circuits for hearing devices are to be able to be deployed for higher frequencies as well. It is therefore proposed according to the invention that at least two PIN diodes should be connected in an anti-parallel manner between the receive oscillating circuit and the amplifier connected thereto to protect the amplifier. A capacitance diode can optionally be expanded so that larger component tolerances can be permitted for the circuit.
摘要翻译：用于听觉设备的结构简单的发送/接收电路也能够被部署用于较高频率。因此，根据本发明提出，至少两个PIN二极管应该以接收振荡电路和与其连接的放大器之间的反并联方式连接，以保护放大器。可以可选地扩展电容二极管，使得电路可以允许更大的组件容差。

6. 发明申请

US20070298712A1 Transmit/receive circuit with PIN diodes 有权
标题翻译：带PIN二极管的发送/接收电路
公开(公告)号：US20070298712A1
公开(公告)日：2007-12-27
申请号：US11823042
申请日：2007-06-26
申请人： Mihail Boguslavskij , Peter Nikles , Jurgen Reithinger , Ulrich Schatzle
发明人： Mihail Boguslavskij , Peter Nikles , Jurgen Reithinger , Ulrich Schatzle
IPC分类号： H04B5/00 , H01Q11/12 , H04B1/16
CPC分类号： H03F1/52 , H03F3/191 , H03F2200/216 , H03F2200/243 , H03F2200/444 , H03F2200/451
摘要： Structurally simple transmit/receive circuits for hearing devices are to be able to be deployed for higher frequencies as well. It is therefore proposed according to the invention that at least two PIN diodes should be connected in an anti-parallel manner between the receive oscillating circuit and the amplifier connected thereto to protect the amplifier. A capacitance diode can optionally be expanded so that larger component tolerances can be permitted for the circuit.
摘要翻译：用于听觉设备的结构简单的发送/接收电路也能够被部署用于较高频率。因此，根据本发明提出，至少两个PIN二极管应该以接收振荡电路和与其连接的放大器之间的反并联方式连接，以保护放大器。可以可选地扩展电容二极管，使得电路可以允许更大的组件容差。

7. 发明申请

US20040080372A1 HIGH FREQUENCY AMPLIFIER 失效
标题翻译：高频放大器
公开(公告)号：US20040080372A1
公开(公告)日：2004-04-29
申请号：US10282000
申请日：2002-10-29
发明人： Yung-Hung Chen
IPC分类号： H03F001/22
CPC分类号： H03F1/223 , H03F2200/213 , H03F2200/222 , H03F2200/243 , H03F2200/378 , H03F2200/387 , H03F2200/399 , H03F2200/414 , H03F2200/421 , H03F2200/492
摘要： A high frequency amplifier. The amplifier includes two transistors for signal amplification, and input and output matching circuits. There are variable capacitors and resistors in the matching input and output circuits. A received signal strength indicator receives the band-pass filtered intermediate-frequency signal and generates an indication signal corresponding to the amplitude of the received signal. The variable capacitors and resistors are tuned by the indication signal from the received signal strength indicator. Thus, the gain of the high frequency amplifier is automatically controlled.
摘要翻译：高频放大器。该放大器包括两个用于信号放大的晶体管，以及输入和输出匹配电路。匹配的输入和输出电路中有可变电容和电阻。接收到的信号强度指示器接收带通滤波的中频信号，并产生与接收信号的振幅相对应的指示信号。可变电容器和电阻器通过来自接收信号强度指示器的指示信号进行调谐。因此，高频放大器的增益被自动控制。

8. 发明申请

US20180083579A1 LNA with Programmable Linearity 有权
公开(公告)号：US20180083579A1
公开(公告)日：2018-03-22
申请号：US15272103
申请日：2016-09-21
申请人： Peregrine Semiconductor Corporation
发明人： Hossein Noori , Chih-Chieh Cheng
IPC分类号： H03F1/32 , H03F1/56 , H03F3/195 , H03G3/00 , H03G3/10
CPC分类号： H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
摘要： A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

9. 发明授权

US09843344B2 Digital variable capacitance circuit, resonant circuit, amplification circuit, and transmitter 有权
公开(公告)号：US09843344B2
公开(公告)日：2017-12-12
申请号：US15187608
申请日：2016-06-20
申请人： Renesas Electronics Corporation
发明人： Masakazu Mizokami
IPC分类号： H04B1/04 , H03H11/32 , H03F3/19 , H03H11/48 , H03H19/00 , H03F3/24
CPC分类号： H04B1/04 , H03F3/19 , H03F3/245 , H03F2200/06 , H03F2200/09 , H03F2200/237 , H03F2200/243 , H03F2200/294 , H03F2200/399 , H03F2200/451 , H03H11/32 , H03H11/481 , H03H19/006 , H04B1/0475
摘要： The present invention aims to provide a digital variable capacitance circuit, a resonant circuit, an amplification circuit, and a transmitter having a high performance. A digital variable capacitance circuit 50 according to this embodiment is a digital variable capacitance circuit including a plurality of unit capacity cells 51-0 to 51-n connected in parallel between two output terminals OUTP and OUTN, in which the unit capacity cell 51 comprises: a first capacitor Cu1 having one end connected to one output terminal OUTP; a second capacitor Cu2 that is connected in series with the first capacitor Cu1 between the two output terminals; and an NMOS transistor M1 that is connected in parallel with the second capacitor Cu2 and is controlled in accordance with a digital control signal.

10. 发明授权

US07688146B2 Single-ended input to differential-ended output low noise amplifier 有权
标题翻译：差分输出低噪声放大器的单端输入
公开(公告)号：US07688146B2
公开(公告)日：2010-03-30
申请号：US11657518
申请日：2007-01-25
申请人： Nien-An Kao , Kwo-Wei Chang
发明人： Nien-An Kao , Kwo-Wei Chang
IPC分类号： H03F3/04
CPC分类号： H03F3/45183 , H03F1/223 , H03F3/19 , H03F2200/108 , H03F2200/243 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2203/45166 , H03F2203/45332 , H03F2203/45631
摘要： A single-ended input to differential-ended output amplifier circuit comprises an amplifier for amplifying an input signal into an amplified signal comprises an input for receiving the input signal; and a first input and a single-ended input to differential-ended output conversion circuit to convert the amplified signal to a differential signal pair, comprising a first transistor for receiving the amplified signal having a first gate coupled to the first output, a first first terminal coupled to a second output, and a first second terminal coupled to a first node; a second transistor having a second gate, a second first terminal coupled to a third input, and a second second terminal coupled to the first node; a second capacitor coupled between the second output and the second gate; a first and a second resistors and the voltage source; and a current source coupled between the first node and a ground.
摘要翻译：差分端输出放大器电路的单端输入包括用于将输入信号放大为放大信号的放大器，包括用于接收输入信号的输入; 以及用于将放大的信号转换成差分信号对的差分端输出转换电路的第一输入和单端输入，包括用于接收具有耦合到第一输出的第一栅极的放大信号的第一晶体管，第一第一终端，耦合到第二输出端，以及耦合到第一节点的第一第二终端; 具有第二栅极的第二晶体管，耦合到第三输入端的第二第一端子和耦合到第一节点的第二第二端子; 耦合在第二输出端和第二栅极之间的第二电容器; 第一和第二电阻器和电压源; 以及耦合在第一节点和地之间的电流源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式