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1. 发明公开

US20240221795A1 DATA CONVERTER FOR CANCELLING OFFSET VOLTAGE 审中-公开
公开(公告)号：US20240221795A1
公开(公告)日：2024-07-04
申请号：US18231935
申请日：2023-08-09
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Youngwoo PARK , Tongsung KIM , Youngmin KIM , Seungjin PARK , Seunghoon LEE , Chaekang LIM , Youngchul CHO , Youngdon CHOI , Junghwan CHOI
IPC分类号： G11C7/10 , H03F3/45 , H03K5/24 , H03M1/06
CPC分类号： G11C7/1048 , H03F3/45475 , H03K5/24 , H03M1/0607 , H03F2200/375 , H03F2203/45044 , H03F2203/45212
摘要： A data converter including an autozeroing circuit including a plurality of gain circuits having a first amplification circuit and a first capacitor connected to the first amplification circuit, the first amplification circuit performing a switch feedthrough offset cancellation operation of storing an offset voltage of the autozeroing circuit in the capacitor through a switch, a comparator circuit including a first input terminal and a second input terminal, the comparator circuit comparing a first input terminal voltage level of the first input terminal with a second input terminal voltage level of the second input terminal, a first switch unit connected between the autozeroing circuit and the comparator circuit, the first switch disconnecting the autozeroing circuit from the comparator circuit during the switch feedthrough offset cancellation operation of the autozeroing circuit, and a second switch unit connected between a first input signal line and a second input signal line.

2. 发明授权

US09966915B2 Programmable amplifier and method of operating the same 有权
公开(公告)号：US09966915B2
公开(公告)日：2018-05-08
申请号：US15222355
申请日：2016-07-28
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Abdullah Ahmed , Frederick Edward Sykes
IPC分类号： H03F1/34 , H03G3/30 , H03F3/45
CPC分类号： H03G3/30 , H03F3/45475 , H03F3/45995 , H03F2200/171 , H03F2203/45044 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G5/28
摘要： A programmable amplifier includes an amplifier, an input capacitor, a feedback circuit, and a high-pass filter circuit. The amplifier has an input coupled to the input capacitor for receiving an input signal. The feedback circuit includes multiple feedback capacitors of differing capacitance values that are each selectively coupled between the output of the amplifier and the input of the amplifier using multiple first switches. The high-pass filter circuit includes multiple switched capacitors of differing capacitance values that are each selectively coupled between the amplifier output and a ground node using multiple second switches. The first switches are configured to be selectively switched on for activating at least one feedback capacitor to adjust a gain of the amplifier, while the second switches are configured to be selectively switched at a first and second phase of a clock signal to adjust a high-pass cutoff frequency of the amplifier independently of how the gain is adjusted.

3. 发明申请

US20180034430A1 PROGRAMMABLE AMPLIFIER AND METHOD OF OPERATING THE SAME 有权
公开(公告)号：US20180034430A1
公开(公告)日：2018-02-01
申请号：US15222355
申请日：2016-07-28
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Abdullah AHMED , Frederick Edward SYKES
IPC分类号： H03G3/30 , H03F3/45
CPC分类号： H03G3/30 , H03F3/45475 , H03F3/45995 , H03F2200/171 , H03F2203/45044 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G5/28
摘要： A programmable amplifier includes an amplifier, an input capacitor, a feedback circuit, and a high-pass filter circuit. The amplifier has an input coupled to the input capacitor for receiving an input signal. The feedback circuit includes multiple feedback capacitors of differing capacitance values that are each selectively coupled between the output of the amplifier and the input of the amplifier using multiple first switches. The high-pass filter circuit includes multiple switched capacitors of differing capacitance values that are each selectively coupled between the amplifier output and a ground node using multiple second switches. The first switches are configured to be selectively switched on for activating at least one feedback capacitor to adjust a gain of the amplifier, while the second switches are configured to be selectively switched at a first and second phase of a clock signal to adjust a high-pass cutoff frequency of the amplifier independently of how the gain is adjusted.

4. 发明申请

US20160079926A1 AMPLIFYING CIRCUIT 有权
标题翻译：放大电路
公开(公告)号：US20160079926A1
公开(公告)日：2016-03-17
申请号：US14855376
申请日：2015-09-15
申请人： LAPIS Semiconductor Co., Ltd.
发明人： Hiroyoshi ICHIKURA , Koji HIGUCHI
IPC分类号： H03F1/02 , H03F3/45
CPC分类号： G09G3/36 , H03F1/0205 , H03F1/303 , H03F3/45 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2203/45044 , H03F2203/45116 , H03F2203/45166
摘要： An amplifying circuit includes a first differential amplifier (first differential pair) and a second differential amplifier (second differential pair) having an input capacitance smaller than the first differential amplifier. The amplifying circuit switches between the first differential amplifier (first differential pair) and the second differential amplifier (second differential pair) in response to an amplification mode setting signal to perform amplification processing of an input signal.
摘要翻译：放大电路包括具有小于第一差分放大器的输入电容的第一差分放大器（第一差分对）和第二差分放大器（第二差分对）。放大电路响应于放大模式设置信号在第一差分放大器（第一差分对）和第二差分放大器（第二差分对）之间切换，以执行输入信号的放大处理。

5. 发明授权

US10082819B2 Switched-capacitor bandgap reference circuit using chopping technique 有权
公开(公告)号：US10082819B2
公开(公告)日：2018-09-25
申请号：US15335367
申请日：2016-10-26
申请人： Marvell World Trade Ltd.
发明人： Weiwei Xu , Prasanna Upadhyaya , Norman Liu , Xiaoyue Wang
IPC分类号： H03K17/00 , G05F3/30 , H03F3/393 , H03F3/45
CPC分类号： G05F3/30 , H03F3/393 , H03F3/45475 , H03F3/45968 , H03F2200/271 , H03F2203/45044 , H03F2203/45286
摘要： A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.

6. 发明申请

US20180091105A1 OPERATION AMPLIFIERS WITH OFFSET CANCELLATION 有权
公开(公告)号：US20180091105A1
公开(公告)日：2018-03-29
申请号：US15278934
申请日：2016-09-28
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： FIRAS N. ABUGHAZALEH
IPC分类号： H03G1/00 , H03F3/45
CPC分类号： H03G1/0088 , H03F3/45183 , H03F3/45192 , H03F3/45766 , H03F3/45775 , H03F2203/45044 , H03F2203/45074 , H03F2203/45288 , H03F2203/45354 , H03F2203/45368 , H03F2203/45396 , H03G1/0029
摘要： A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.

7. 发明申请

US20180062588A1 FBDDA AMPLIFIER AND DEVICE INCLUDING THE FBDDA AMPLIFIER 审中-公开
公开(公告)号：US20180062588A1
公开(公告)日：2018-03-01
申请号：US15790518
申请日：2017-10-23
申请人： STMicroelectronics S.r.l.
发明人： Andrea Barbieri , Sergio Pernici
IPC分类号： H03F1/32 , H03F3/45 , H04R3/00 , H04R19/00 , H04R19/04
CPC分类号： H03F1/3211 , H03F3/45197 , H03F3/45273 , H03F3/45708 , H03F2200/261 , H03F2203/45044 , H03F2203/45101 , H03F2203/45116 , H03F2203/45136 , H03F2203/45151 , H03F2203/45156 , H03F2203/45361 , H03F2203/45492 , H03F2203/45506 , H04R3/00 , H04R19/005 , H04R19/04 , H04R2201/003
摘要： A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.

8. 发明申请

US20170115684A1 SWITCHED-CAPCITOR BANDGAP REFERENCE CIRCUIT USING CHOPPING TECHNIQUE 审中-公开
公开(公告)号：US20170115684A1
公开(公告)日：2017-04-27
申请号：US15335367
申请日：2016-10-26
申请人： Marvell World Trade Ltd.
发明人： Weiwei XU , Prasanna UPADHYAYA , Norman LIU , Xiaoyue WANG
IPC分类号： G05F3/30 , H03F3/45 , H03F3/393
CPC分类号： G05F3/30 , H03F3/393 , H03F3/45475 , H03F3/45968 , H03F2200/271 , H03F2203/45044 , H03F2203/45286
摘要： A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.

9. 发明申请

US20160156319A1 FBDDA AMPLIFIER AND DEVICE INCLUDING THE FBDDA AMPLIFIER 有权
标题翻译： FBDDA放大器和器件，包括FBDDA放大器
公开(公告)号：US20160156319A1
公开(公告)日：2016-06-02
申请号：US14863184
申请日：2015-09-23
申请人： STMicroelectronics S.r.l.
发明人： Andrea Barbieri , Sergio Pernici
IPC分类号： H03F1/32 , H04R3/00 , H03F3/45
CPC分类号： H03F1/3211 , H03F3/45197 , H03F3/45273 , H03F3/45708 , H03F2200/261 , H03F2203/45044 , H03F2203/45101 , H03F2203/45116 , H03F2203/45136 , H03F2203/45151 , H03F2203/45156 , H03F2203/45361 , H03F2203/45492 , H03F2203/45506 , H04R3/00 , H04R19/005 , H04R19/04 , H04R2201/003
摘要： A FBDDA amplifier comprising: a first differential input stage, which receives an input voltage; a second differential input stage, which receives a common-mode voltage; a first resistive-degeneration group coupled to the first differential input; a second resistive-degeneration group coupled to the second differential input; a differential output stage, generating an output voltage; a first switch coupled in parallel to the first resistive-degeneration group; and a second switch coupled in parallel to the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.
摘要翻译：一种FBDDA放大器，包括：第一差分输入级，其接收输入电压; 第二差分输入级，其接收共模电压; 耦合到所述第一差分输入的第一电阻变性组; 耦合到所述第二差分输入的第二电阻变性组; 差分输出级，产生输出电压; 与第一电阻变性组并联耦合的第一开关; 以及与第二电阻变性组并联耦合的第二开关。当电压输入为第一值时，第一和第二开关被驱动到关闭状态，使得所述第一输入级在线性区域中工作，并且当电压输入为第二值时被驱动到打开状态，高于第一值，使得第一输入级在非线性区域中操作。

10. 发明申请

US20160142019A1 AMPLIFYING DEVICE AND OFFSET VOLTAGE CORRECTION METHOD 有权
标题翻译：放大器件和偏置电压校正方法
公开(公告)号：US20160142019A1
公开(公告)日：2016-05-19
申请号：US14884209
申请日：2015-10-15
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motomitsu IWAMOTO
IPC分类号： H03F1/02 , H03F3/217 , H03F3/45 , H03F3/21
CPC分类号： H03F3/2173 , H03F3/45183 , H03F3/45771 , H03F2200/375 , H03F2203/45044 , H03F2203/45674
摘要： An output voltage delay time caused by the relationship between offset voltage and input voltage is shortened. A single power supply amplifying device includes first and second amplifying units, a state detecting unit, and an offset voltage correcting unit. The first amplifying unit has differential pair transistors and amplifies the difference between input voltages. The second amplifying unit amplifies a first output voltage of the first amplifying unit. The state detecting unit detects a state where a negative offset voltage that causes a second output voltage of the second amplifying unit to be lower than the input voltage occurs, and a potential of the input voltage is lower than the absolute value of the negative offset voltage. The offset voltage correcting unit then corrects the negative offset voltage to a positive offset voltage that causes the second output voltage to be higher than the input voltage.
摘要翻译：由偏移电压和输入电压之间的关系引起的输出电压延迟时间缩短。单个电源放大装置包括第一和第二放大单元，状态检测单元和偏移电压校正单元。第一放大单元具有差分对晶体管并且放大输入电压之间的差。第二放大单元放大第一放大单元的第一输出电压。状态检测单元检测使发生第二放大单元的第二输出电压的负偏移电压低于输入电压的状态，并且输入电压的电位低于负偏移电压的绝对值。偏移电压校正单元将负偏移电压校正为使得第二输出电压高于输入电压的正偏移电压。

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