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1. 发明授权

US08294489B2 Programmable logic circuit 有权
标题翻译：可编程逻辑电路
公开(公告)号：US08294489B2
公开(公告)日：2012-10-23
申请号：US12404606
申请日：2009-03-16
申请人： Tetsufumi Tanamoto , Hideyuki Sugiyama , Kazutaka Ikegami , Yoshiaki Saito
发明人： Tetsufumi Tanamoto , Hideyuki Sugiyama , Kazutaka Ikegami , Yoshiaki Saito
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G11C13/0002 , H03K19/17764 , H03K19/1778 , H03K19/17784 , H03K19/18
摘要： A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.
摘要翻译：可编程逻辑电路包括：输入电路，被配置为接收多个输入信号; 以及包括以矩阵形式布置的多个单元可编程单元的可编程单元阵列，每个单元可编程单元包括电阻改变型的第一存储器电路，包括第一晶体管和包括第二晶体管的电阻变化型的第二存储器电路并联连接的第一和第二存储器电路，同一行上的第一晶体管的每个栅极分别接收一个输入信号，同一行上的第二晶体管的每个栅极接收一个输入信号的反相信号，第一个输出端的输出端并且同一列上的第二存储器电路连接到公共输出线。

2. 发明授权

US08154916B2 Nonvolatile memory circuit using spin MOS transistors 有权
标题翻译：使用自旋MOS晶体管的非易失性存储电路
公开(公告)号：US08154916B2
公开(公告)日：2012-04-10
申请号：US12889881
申请日：2010-09-24
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： G11C11/14
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译：某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

3. 发明申请

US20120074984A1 LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：查看表电路和现场可编程门阵列
公开(公告)号：US20120074984A1
公开(公告)日：2012-03-29
申请号：US13238020
申请日：2011-09-21
申请人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K19/177 , H03K5/00
CPC分类号： H03K19/177
摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
摘要翻译：根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。

4. 发明授权

US07653855B2 Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device 有权
标题翻译：随机数测试电路，随机数生成电路，半导体集成电路，IC卡和信息终端设备
公开(公告)号：US07653855B2
公开(公告)日：2010-01-26
申请号：US11875360
申请日：2007-10-19
申请人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
发明人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F7/58 , G01R31/3181
摘要： A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.
摘要翻译：随机数测试电路包括：计数单元，用于对随机数序列中的特定值比特的重复次数进行计数，串联发生的重复;检测单元，用于检测与随机数中的比特种类对应的多个数字数字序列，以及基于该数字确定随机数序列是否正常的确定单元。

5. 发明申请

US20090309646A1 RANDOM NUMBER GENERATION DEVICE 审中-公开
标题翻译：随机数生成装置
公开(公告)号：US20090309646A1
公开(公告)日：2009-12-17
申请号：US12391640
申请日：2009-02-24
申请人： Shigeki KOBAYASHI , Ken Uchida , Shinobu Fujita , Tetsufumi Tanamoto
发明人： Shigeki KOBAYASHI , Ken Uchida , Shinobu Fujita , Tetsufumi Tanamoto
IPC分类号： G06G7/12 , H01L27/088
CPC分类号： H01L29/1054 , G06F7/588 , H01L21/823807 , H01L27/088 , H01L29/7843 , H03K3/84
摘要： A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film.
摘要翻译：随机数生成装置包括：第一源区域; 第一漏区; 设置在所述第一源极区域和所述第一漏极区域之间的第一沟道区域; 设置在所述第一沟道区上的第一绝缘膜; 以及设置在第一绝缘膜上的第一栅电极。第一绝缘膜具有陷阱捕获和释放电荷，并且在栅极长度方向上向第一沟道区和第一绝缘膜中的至少一个施加拉伸或压缩应力。

6. 发明申请

US20080256152A1 RANDOM NUMBER GENERATING DEVICE 有权
公开(公告)号：US20080256152A1
公开(公告)日：2008-10-16
申请号：US12143206
申请日：2008-06-20
申请人： Tetsufumi Tanamoto , Shinobu Fujita
发明人： Tetsufumi Tanamoto , Shinobu Fujita
IPC分类号： G06F7/58
CPC分类号： B82Y10/00 , G06F7/588 , H01L29/7888 , H04L9/0861
摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

7. 发明申请

US20080251783A1 RANDOM NUMBER GENERATING DEVICE 失效
标题翻译：随机数生成装置
公开(公告)号：US20080251783A1
公开(公告)日：2008-10-16
申请号：US12143124
申请日：2008-06-20
申请人： Tetsufumi TANAMOTO , Shinobu Fujita
发明人： Tetsufumi TANAMOTO , Shinobu Fujita
IPC分类号： H01L29/00
CPC分类号： B82Y10/00 , G06F7/588 , H01L29/7888 , H04L9/0861
摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.
摘要翻译：目的是提供具有较小的电路尺寸和较小的输出偏压值的随机数产生装置。随机数产生装置包括彼此平行布置的一对第一和第二电流路径，以及一对可互相交换电荷并位于第一和第二电流路径附近的第一和第二细颗粒。

8. 发明申请

US20130076551A1 ANALOG-TO-DIGITAL CONVERTER 失效
标题翻译：模拟数字转换器
公开(公告)号：US20130076551A1
公开(公告)日：2013-03-28
申请号：US13535118
申请日：2012-06-27
申请人： Takao MARUKAME , Tetsufumi Tanamoto , Atsuhiro Kinoshita , Tomoaki Inokuchi , Masamichi Suzuki , Yoshiaki Saito
发明人： Takao MARUKAME , Tetsufumi Tanamoto , Atsuhiro Kinoshita , Tomoaki Inokuchi , Masamichi Suzuki , Yoshiaki Saito
IPC分类号： H03M1/36
CPC分类号： H03M1/1061 , H03F3/45183 , H03F2203/45391 , H03F2203/45392 , H03F2203/45674 , H03K5/2481 , H03M1/365
摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.
摘要翻译：根据实施例，模数转换器包括产生比较电压的电压产生单元; 和比较者。每个比较器将比较电压中的任何一个与模拟输入电压进行比较，并输出数字信号。每个比较器包括用于检测两个输入之间的电位差的差分对电路。差分对电路包括第一和第二电路部分。第一电路部分包括具有一个输入端的栅极的第一晶体管; 以及与第一晶体管串联连接的电阻器。第二电路部分包括第二晶体管，其具有提供另一输入的栅极，并与第一晶体管形成差分对; 以及与第二晶体管串联连接的可变电阻器。可变电阻器包括可变电阻元件，每个电阻元件具有根据控制信号可变地设置的电阻值。

9. 发明授权

US08330160B2 Random number generating device 有权
标题翻译：随机数生成装置
公开(公告)号：US08330160B2
公开(公告)日：2012-12-11
申请号：US12143206
申请日：2008-06-20
申请人： Tetsufumi Tanamoto , Shinobu Fujita
发明人： Tetsufumi Tanamoto , Shinobu Fujita
IPC分类号： H01L23/58
CPC分类号： B82Y10/00 , G06F7/588 , H01L29/7888 , H04L9/0861
摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.
摘要翻译：目的是提供具有较小电路尺寸和较小输出偏置值的随机数产生装置。随机数产生装置包括彼此平行布置的一对第一和第二电流路径，以及一对可互相交换电荷并位于第一和第二电流路径附近的第一和第二细颗粒。

10. 发明申请

US20120243336A1 NONVOLATILE PROGRAMMABLE LOGIC SWITCH 有权
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US20120243336A1
公开(公告)日：2012-09-27
申请号：US13240087
申请日：2011-09-22
申请人： Yoshifumi NISHI , Daisuke HAGISHIMA , Shinichi YASUDA , Tetsufumi TANAMOTO , Takahiro KURITA , Atsuhiro KINOSHITA , Shinobu FUJITA
发明人： Yoshifumi NISHI , Daisuke HAGISHIMA , Shinichi YASUDA , Tetsufumi TANAMOTO , Takahiro KURITA , Atsuhiro KINOSHITA , Shinobu FUJITA
IPC分类号： G11C16/10 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0458 , G11C16/10 , H01L27/11573 , H01L27/11803
摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.
摘要翻译：本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

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