专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120037994A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120037994A1
公开(公告)日：2012-02-16
申请号：US13283264
申请日：2011-10-27
申请人： Masumi SAITOH , Ken UCHIDA
发明人： Masumi SAITOH , Ken UCHIDA
IPC分类号： H01L27/092
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L29/0673 , H01L29/0676 , H01L29/66795 , H01L29/7842 , H01L29/7843
摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.
摘要翻译：提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管以及用于实现其的SMT引入制造方法。半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区，在其间插入通道区域。通道区域在与基板主平面垂直的方向上施加压缩应变。还公开了该装置的制造方法。

2. 发明授权

US07737486B2 Non-volatile semiconductor storage device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US07737486B2
公开(公告)日：2010-06-15
申请号：US11859142
申请日：2007-09-21
申请人： Masumi Saitoh , Ken Uchida
发明人： Masumi Saitoh , Ken Uchida
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/165 , H01L29/7881
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变，并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

3. 发明申请

US20090242990A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090242990A1
公开(公告)日：2009-10-01
申请号：US12401704
申请日：2009-03-11
申请人： Masumi SAITOH , Ken UCHIDA
发明人： Masumi SAITOH , Ken UCHIDA
IPC分类号： H01L27/092 , H01L21/28 , H01L21/20
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L29/0673 , H01L29/0676 , H01L29/66795 , H01L29/7842 , H01L29/7843
摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.
摘要翻译：提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管，以及用于实现其的SMT引入制造方法。半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区，在其间插入通道区域。通道区域在与基板主平面垂直的方向上施加压缩应变。还公开了该装置的制造方法。

4. 发明授权

US07144002B2 Electric locking device 有权
标题翻译：电锁装置
公开(公告)号：US07144002B2
公开(公告)日：2006-12-05
申请号：US10862422
申请日：2004-06-08
申请人： Kai Zhao , Erick Rudaitis , David Ken Uchida , Jeffrey Gerald Kozlowski
发明人： Kai Zhao , Erick Rudaitis , David Ken Uchida , Jeffrey Gerald Kozlowski
IPC分类号： B23Q3/08
CPC分类号： B25B5/08 , B25B5/087
摘要： The present invention provides an electric locking device which has a simple structure, with which an operating time can be saved, and which has a sufficient clamping force required for operation. To a camshaft coupled to an electric motor through a speed reducing mechanism, a first cam and a second cam conjugate with each other are coupled. The first cam drives an arm driving rod in a clamping direction and the second cam drives the arm driving rod in a returning direction. Rotational motions of the first and second cams are converted into linear motions in the same direction by first and second cam contacting members supported by the arm driving rod. The arm driving rod drives a clamping arm to cause the arm to carry out a clamping operation. A cam face is provided as to move the clamping arm at a high speed until the arm reaches a vicinity of an end and to move the arm at a lower speed after the arm has reached the vicinity of the end.
摘要翻译：本发明提供一种具有简单结构的电锁装置，能够节省操作时间，并具有足够的操作所需的夹紧力。通过减速机构联接到电动机的凸轮轴，彼此耦合的第一凸轮和第二凸轮共轭。第一凸轮沿夹紧方向驱动臂驱动杆，第二凸轮沿返回方向驱动臂驱动杆。通过由臂驱动杆支撑的第一和第二凸轮接触构件将第一和第二凸轮的旋转运动转换成相同方向的线性运动。臂驱动杆驱动夹紧臂使臂进行夹紧操作。凸轮面设置成以高速移动夹持臂，直到臂到达端部附近并且在臂已经到达端部附近之后以较低的速度移动臂。

5. 发明授权

US06690030B2 Semiconductor device with negative differential resistance characteristics 失效
标题翻译：具有负差分电阻特性的半导体器件
公开(公告)号：US06690030B2
公开(公告)日：2004-02-10
申请号：US09798923
申请日：2001-03-06
申请人： Junji Koga , Ken Uchida , Ryuji Ohba , Akira Toriumi
发明人： Junji Koga , Ken Uchida , Ryuji Ohba , Akira Toriumi
IPC分类号： H01L2940
CPC分类号： H01L27/1104 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/511 , H01L29/7881
摘要： A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load. The negative differential resistance and the load are serially connected together between a low-voltage power supply (ground potential) Vss and a high-voltage power supply Vdd, thus enabling forming a transistor with a built-in bistable circuit. Potential information of the first polysilicon film for use as a data storage node is read with a transistor amplification applied thereto. Thus, data read is performed at high speeds. Simultaneously, a current flowing between the power supplies is suppressed to a lower level, thereby minimizing power consumption in wait modes.
摘要翻译：形成在硅衬底表面上的栅极氧化膜的厚度部分地减小或者在其源区域上的指定部分“薄化”。在栅极区域中，以层叠的顺序形成包括p型导电体的第一多晶硅或“多晶硅”膜，隧道氧化物膜和第二p型多晶硅膜的多层结构。源极区域和第一多晶硅膜构成了高浓度杂质掺杂的pn结，其间铺设有薄的氧化硅膜，提供了也称为Esaki二极管的隧道二极管。二极管用于负差分电阻。此外，第一和第二多晶硅膜之间的部分是用作负载的非线性隧道电阻器。负的差分电阻和负载在低压电源（接地电位）Vss和高压电源Vdd之间串联连接在一起，从而能够形成具有内置双稳态电路的晶体管。读取用作数据存储节点的第一多晶硅膜的电位信息，并施加晶体管放大。因此，高速执行数据读取。同时，在电源之间流动的电流被抑制到较低的电平，从而使等待模式中的功耗最小化。

6. 发明授权

US5068267A Semiconductor device encapsulant consisting of epoxy resin composition 失效
标题翻译：环氧树脂组合物的半导体器件封装
公开(公告)号：US5068267A
公开(公告)日：1991-11-26
申请号：US405533
申请日：1989-09-12
申请人： Ken Uchida , Michiya Higashi , Naoko Kihara , Hiroshi Shimozawa , Akira Yoshizumo
发明人： Ken Uchida , Michiya Higashi , Naoko Kihara , Hiroshi Shimozawa , Akira Yoshizumo
IPC分类号： C08L61/06 , C08G59/00 , C08G59/32 , C08G59/62 , C08L61/04 , C08L63/00 , H01L23/29 , H01L23/31
CPC分类号： H01L23/293 , C08G59/3218 , C08L63/00 , H01L2924/0002
摘要： An encapsulant consisting of an epoxy resin composition and suitably used to encapsulate a semiconductor device which is to be surface-mounted contains(a) an epoxy resin,(b) a rubber-modified phenolic resin comprising a phenolic resin, and a methylmethacrylate-butadiene-styrene copolymer and a thermosetting silicon rubber dispersed in said phenolic resin,(c) a curing accelerator, and(d) a silica powder.

7. 发明授权

US4630086A Nonvolatile MNOS memory 失效
标题翻译：非易失性MNOS存储器
公开(公告)号：US4630086A
公开(公告)日：1986-12-16
申请号：US535233
申请日：1983-09-23
申请人： Nobuyuki Sato , Kyotake Uchiumi , Shinji Nabetani , Ken Uchida
发明人： Nobuyuki Sato , Kyotake Uchiumi , Shinji Nabetani , Ken Uchida
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/02 , H01L29/34
CPC分类号： G11C16/0433 , G11C16/0466 , H01L29/7883
摘要： A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.
摘要翻译：公开了一种非易失性存储器，其具有浮动型EEPROM和MNOS型EEPROM的优点，并且能够以低电压写入和擦除。非易失性存储器中的每个存储元件具有浮置栅极，控制栅极，半导体主体和浮置栅极之间的栅极绝缘膜，以及控制栅极和浮动栅极之间的层间绝缘膜。栅极绝缘膜由非常薄的SiO 2膜和形成在其上的薄的Si 3 N 4膜构成。注入用于存储数据的电荷的电荷重心位于浮动栅极内，而不在Si3N4膜内。

8. 发明授权

US08039887B2 Non-volatile semiconductor storage device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US08039887B2
公开(公告)日：2011-10-18
申请号：US12773967
申请日：2010-05-05
申请人： Masumi Saitoh , Ken Uchida
发明人： Masumi Saitoh , Ken Uchida
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/165 , H01L29/7881
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变，并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

9. 发明申请

US20090242986A1 MULTI-GATE FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：多门场效应晶体管及其制造方法
公开(公告)号：US20090242986A1
公开(公告)日：2009-10-01
申请号：US12210328
申请日：2008-09-15
申请人： Yukio NAKABAYASHI , Ken UCHIDA
发明人： Yukio NAKABAYASHI , Ken UCHIDA
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.
摘要翻译：多栅极场效应晶体管包括：平行布置在衬底上的多个半导体层; 形成在每个半导体层中的源区和漏区; 沟道区域，每个沟道区域设置在每个半导体层中的源极区域和漏极区域之间; 保护膜分别设置在每个通道区域的上表面上; 栅极绝缘膜各自设置在每个沟道区域的两个侧面上; 设置在每个沟道区域的两个侧面上的多个栅电极，以便设置在每个沟道区域的上表面上方的栅极绝缘膜，以便插入保护膜，并且容纳金属元件; 连接所述栅电极的上表面的连接部; 以及连接到连接部分的栅极线。

10. 发明授权

US07057302B2 Static random access memory 失效
标题翻译：静态随机存取存储器
公开(公告)号：US07057302B2
公开(公告)日：2006-06-06
申请号：US10909399
申请日：2004-08-03
申请人： Kazuya Matsuzawa , Ken Uchida , Takahiro Nakauchi
发明人： Kazuya Matsuzawa , Ken Uchida , Takahiro Nakauchi
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/1104 , H01L27/1463 , Y10S257/903
摘要： A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode. The gate electrode shared by the first and second complementary field-effect transistors is connected to the common drain region of the mutually opposing complementary field-effect transistors, and the static random access memory has superior resistance to software errors.
摘要翻译：一种静态随机存取存储器具有第一和第二互补型场效应晶体管。第一互补场效应晶体管包括：半导体衬底，电子传导类型的第一场效应晶体管，其具有构成肖特基结和栅电极的第一漏极区，和正空穴传导类型的第一场效应晶体管，其共享第一漏极区，设有一个共用栅电极。所述第二互补型场效应晶体管包括电子传导类型的第二场效应晶体管，其具有第二漏区和栅电极，正空穴传导类型的这股第二漏区，并具有一共享的第二场效应晶体管栅电极。由第一和第二互补场效应晶体管共享栅电极被连接到彼此相对的互补型场效应晶体管的公共漏极区和静态随机存取存储器具有软件错误优异。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式