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1. 发明授权

US09806068B2 Semiconductor device 有权
公开(公告)号：US09806068B2
公开(公告)日：2017-10-31
申请号：US15417243
申请日：2017-01-27
申请人： FUJI ELECTRIC CO., LTD.
发明人： Katsunori Ueno
IPC分类号： H01L29/74 , H01L25/18 , H01L29/739 , H01L29/16 , H01L29/20 , H01L23/31
CPC分类号： H01L25/18 , H01L23/3114 , H01L29/1608 , H01L29/2003 , H01L29/7392 , H01L29/7396 , H01L29/74 , H01L29/7802 , H01L2224/01 , H01L2924/15174
摘要： Inside an IGBT using GaN or SiC, light having an energy of approximately 3 [eV] is generated. Therefore, defects are caused in the gate insulating film of the IGBT. Furthermore, the charge trapped at a deep level becomes excited and moves to the channel region, thereby causing the gate threshold voltage to fluctuate from the predetermined value. Provided is a semiconductor device including a normally-ON semiconductor element that includes a first semiconductor layer capable of conductivity modulation and a first gate electrode, but does not include a gate insulating film between the first gate electrode and the first semiconductor layer; and a normally-OFF semiconductor element that includes a second semiconductor layer, a second gate electrode, and a gate insulating film between the second semiconductor layer and the second gate electrode. The normally-ON semiconductor element and the normally-OFF semiconductor element are connected in series.

2. 发明申请

US20160163806A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：US20160163806A1
公开(公告)日：2016-06-09
申请号：US14929912
申请日：2015-11-02
申请人： FUJI ELECTRIC CO., LTD.
发明人： Takeyoshi NISHIMURA
IPC分类号： H01L29/417 , H01L29/10 , H01L23/00 , H01L29/78
CPC分类号： H01L29/41741 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L29/1095 , H01L29/417 , H01L29/66348 , H01L29/66356 , H01L29/7392 , H01L29/7397 , H01L29/7813 , H01L2224/05083 , H01L2224/05166 , H01L2224/05171 , H01L2224/0518 , H01L2224/05184 , H01L2224/05559 , H01L2224/05624 , H01L2224/45015 , H01L2224/45124 , H01L2224/48455 , H01L2224/4847 , H01L2224/85205 , H01L2924/00014 , H01L2924/3512 , H01L2924/2076 , H01L2924/01028 , H01L2924/01014 , H01L2924/01029 , H01L2924/01012 , H01L2924/0103 , H01L2924/013 , H01L2924/01008
摘要： A deterioration of a gate threshold voltage, which is caused by a stress and a thermal hysteresis when wire bonding for a surface of an electrode layer of a semiconductor device is performed, can be suppressed. The semiconductor device includes a metallic film provided at a surface of a semiconductor chip, and a wire bonded to an upper surface of the metallic film. The metallic film has a plurality of grains, particle diameters of the grains are substantially equal to or more than a thickness of the metallic film.
摘要翻译：可以抑制在执行半导体器件的电极层的表面的引线接合时由应力和热滞后引起的栅极阈值电压的劣化。半导体器件包括设置在半导体芯片的表面的金属膜和与金属膜的上表面接合的引线。金属膜具有多个晶粒，粒子的粒径基本上等于或大于金属膜的厚度。

3. 发明授权

US08685812B2 Logic switch and circuits utilizing the switch 有权
标题翻译：逻辑开关和电路利用开关
公开(公告)号：US08685812B2
公开(公告)日：2014-04-01
申请号：US13731744
申请日：2012-12-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Min-Hwa Chi
IPC分类号： H01L29/94
CPC分类号： H01L29/66477 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/7392
摘要： A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.
摘要翻译：逻辑开关有意利用GIDL电流作为其主要操作机制。电压可以施加到覆盖并与pn结绝缘的掺杂栅极。第一个电压启动GIDL电流，并且逻辑开关是双向导电的。第二个电压终止GIDL电流，但逻辑开关是单向导通的。第三个电压使逻辑开关双向不导通。还描述了包含逻辑开关的电路。这些电路包括逆变器，SRAM单元，电压参考源和神经元逻辑开关。逻辑开关主要根据SOI协议实现，但是描述了根据批量协议的实施例。

4. 发明申请

US20140055901A1 SOLID STATE FAULT ISOLATION DEVICES AND METHODS 审中-公开
标题翻译：固态故障隔离装置和方法
公开(公告)号：US20140055901A1
公开(公告)日：2014-02-27
申请号：US13975970
申请日：2013-08-26
申请人： North Carolina State University
发明人： Woongje Sung , Qin Huang , Bantval Jayant Baliga
IPC分类号： H01L29/808
CPC分类号： H01L29/808 , H01L27/0248 , H01L29/0839 , H01L29/102 , H01L29/1608 , H01L29/42308 , H01L29/7392 , H01L29/744 , H01L29/8083
摘要： Disclosed herein are solid state fault isolation devices and methods. According to one or more embodiments, a semiconductor current fault controlled device is provided. The device includes a semiconductor substrate of N-type conductivity. The substrate has opposed major surfaces. An anode region of P-type conductivity is formed in one major surface. A P-type buried layer is formed in a first portion of the other major surface. A junction field-effect transistor (JFET) is formed in a second portion of the other major surface. A P-type top layer is formed in the JFET and forms a channel defined by an overlap between the P-type buried layer and the P-type top layer. The channel laterally extends to the semiconductor substrate from a cathode region and being shielded from the anode region.
摘要翻译：这里公开了固态故障隔离装置和方法。根据一个或多个实施例，提供半导体电流故障控制装置。该器件包括N型导电性的半导体衬底。衬底具有相对的主表面。在一个主表面上形成P型导电性的阳极区域。 P型掩埋层形成在另一个主表面的第一部分中。在另一个主表面的第二部分中形成结型场效应晶体管（JFET）。在JFET中形成P型顶层，并形成由P型掩埋层和P型顶层之间的重叠界定的沟道。通道从阴极区域横向延伸到半导体衬底并且被屏蔽到阳极区域。

5. 发明申请

US20130161691A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130161691A1
公开(公告)日：2013-06-27
申请号：US13721409
申请日：2012-12-20
申请人： NGK Insulators, Ltd.
发明人： Shoji YOKOI , Naohiro SHIMIZU , Masakazu KIMURA
IPC分类号： H01L29/74
CPC分类号： H01L29/74 , H01L29/1066 , H01L29/7392
摘要： A semiconductor device contains a semiconductor substrate, a cathode, an anode, and a gate electrode. The semiconductor device has a cathode segment disposed in a portion corresponding to at least the cathode, an anode segment disposed in a portion corresponding to the anode, a plurality of embedded segments disposed in a portion closer to the cathode segment than to the anode segment, a takeoff segment disposed between the gate electrode and the embedded segments to electrically connect the gate electrode to the embedded segments, and a channel segment disposed between the adjacent embedded segments.
摘要翻译：半导体器件包含半导体衬底，阴极，阳极和栅电极。半导体器件具有设置在至少对应于阴极的部分中的阴极段，设置在与阳极相对应的部分中的阳极段，多个嵌入段设置在比阳极段更靠近阴极段的部分中，设置在所述栅电极和所述嵌入段之间以将所述栅电极与所述嵌入段电连接的起飞段以及设置在所述相邻嵌入段之间的通道段。

6. 发明申请

US20090008650A1 FIELD-EFFECT TRANSISTOR AND THYRISTOR 审中-公开
标题翻译：场效应晶体管和晶体管
公开(公告)号：US20090008650A1
公开(公告)日：2009-01-08
申请号：US12182816
申请日：2008-07-30
申请人： Makoto MIZUKAMI , Takashi Shinohe
发明人： Makoto MIZUKAMI , Takashi Shinohe
IPC分类号： H01L29/24
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/167 , H01L29/66068 , H01L29/7392 , H01L29/7828 , H01L29/8083
摘要： A decrease in breakdown voltage can be prevented as much as possible. A field-effect transistor includes: a drain region made of SiC; a drift layer which is formed on the drain region and is made of n-type SiC; a source region which is formed on the surface of the drift layer and is made of n-type SiC; a channel region which is formed on the surface of the drift layer located on a side of the source region and is made of SiC; an insulating gate which is formed on the channel region; and a p-type base region interposed between the bottom portion of the source region and the drift region, and containing two kinds of p-type impurities.
摘要翻译：可以尽可能地防止击穿电压的降低。场效应晶体管包括：由SiC制成的漏区; 漂移层，其形成在漏区，由n型SiC制成; 源区，其形成在漂移层的表面上并由n型SiC制成; 沟道区，形成在位于源极区一侧的漂移层的表面上并由SiC制成; 形成在沟道区上的绝缘栅; 以及插入在源极区域的底部与漂移区域之间的p型基极区域，并且含有两种p型杂质。

7. 发明授权

US07205629B2 Lateral super junction field effect transistor 有权
标题翻译：横向超结场效应晶体管
公开(公告)号：US07205629B2
公开(公告)日：2007-04-17
申请号：US10859564
申请日：2004-06-03
申请人： Ranbir Singh
发明人： Ranbir Singh
IPC分类号： H01L23/58
CPC分类号： H01L29/1602 , H01L29/1066 , H01L29/1608 , H01L29/7392 , H01L29/808 , H01L2924/0002 , H03K17/567 , H01L2924/00
摘要： A voltage booster transistor with an optimal conducting path formed in widebandgap semiconductors like Silicon Carbide and Diamond, is provided as a power transistor with a voltage rating >200V. Contrary to conventional vertical design of power transistors, a higher, optimum doping for a given thickness supports higher Source/Drain blocking voltage. A topside and backside gate region of the opposite conductivity type than the channel region providing control of source to drain current path through a small gate voltage. The backside gate and the Drain junction are able to support the rated blocking voltage of the device.
摘要翻译：具有形成在诸如碳化硅和金刚石之类的宽带隙半导体中的最佳导电路径的升压晶体管被提供为具有额定电压> 200V的功率晶体管。与功率晶体管的常规垂直设计相反，给定厚度的更高的最佳掺杂支持更高的源极/漏极阻塞电压。与沟道区相反的导电类型的上侧和后侧栅极区域提供通过小栅极电压的源极到漏极电流路径的控制。背面栅极和漏极结能够支持器件的额定阻断电压。

8. 发明申请

US20060081964A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060081964A1
公开(公告)日：2006-04-20
申请号：US11224680
申请日：2005-09-12
申请人： Frank Pfirsch
发明人： Frank Pfirsch
IPC分类号： H01L27/082
CPC分类号： H01L29/7394 , H01L29/0839 , H01L29/7392 , H01L29/7395
摘要： A semiconductor device (1, 20-80) has an emitter terminal (2), a collector terminal (3) and also a semiconductor body (4) provided between emitter terminal (2) and collector terminal (3). An emitter zone (5, 70) is formed in the semiconductor body (4), said emitter zone at least partially adjoining the emitter terminal (2) and also having a first interface (16) facing the emitter terminal (2) and a second interface (17) facing the collector terminal. The semiconductor device has at least one MOS structure (8, 81) which pervades the emitter zone or adjoins the latter, and which is configured such that corresponding MOS channels (11, 14) induced by the MOS structure (8, 81) within the emitter zone (5, 70) are at a distance from the first interface (16) of the emitter zone (5, 70).
摘要翻译：半导体器件（1-20-80）具有发射极端子（2），集电极端子（3）以及设置在发射极端子（2）和集电极端子（3）之间的半导体本体（4）。在半导体本体（4）中形成发射区（5,70），所述发射极区至少部分邻接发射极端（2），并且还具有面向发射极端（2）的第一界面（16）接口（17）面对集电极端子。半导体器件具有至少一个覆盖发射区或与之相邻的MOS结构（8,81），并且被配置为使得由MOS结构（8,81）引起的对应的MOS沟道（11,14）发射极区（5,70）距离发射区（5,70）的第一界面（16）一定距离。

9. 发明申请

US20060033128A1 Logic switch and circuits utilizing the switch 有权
公开(公告)号：US20060033128A1
公开(公告)日：2006-02-16
申请号：US10916190
申请日：2004-08-11
申请人： Min-Hwa Chi
发明人： Min-Hwa Chi
IPC分类号： H01L29/80
CPC分类号： H01L29/66477 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/7392
摘要： A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

10. 发明申请

US20050269661A1 Lateral channel transistor 失效
标题翻译：侧向通道晶体管
公开(公告)号：US20050269661A1
公开(公告)日：2005-12-08
申请号：US10859576
申请日：2004-06-03
申请人： Ranbir Singh
发明人： Ranbir Singh
IPC分类号： H01L29/15 , H01L29/739 , H01L29/808 , H01L31/0312
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1608 , H01L29/7392 , H03K17/567
摘要： A lateral channel transistor with an optimal conducting channel formed in widebandgap semiconductors like Silicon Carbide and Diamond is provided. Contrary to conventional vertical design of power transistors, a higher, optimum doping for a given thickness supports higher source/drain blocking voltage. A backside gate is insulated from the channel region using a low doped layer of the opposite conductivity type than the channel region to support the rated blocking voltage of the device.
摘要翻译：提供了一种在诸如碳化硅和金刚石之类的宽带隙半导体中形成的具有最佳导电沟道的横向沟道晶体管。与功率晶体管的常规垂直设计相反，给定厚度的更高，最佳掺杂支持更高的源/漏阻挡电压。使用与沟道区相反的导电类型的低掺杂层与沟道区绝缘，以支持器件的额定阻断电压。

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