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1. 发明申请

US20160240666A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160240666A1
公开(公告)日：2016-08-18
申请号：US14717526
申请日：2015-05-20
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toshitaka MIYATA , Yoshiyuki KONDO
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/423 , H01L29/40
CPC分类号： H01L29/0847 , H01L29/0834 , H01L29/42368 , H01L29/7391
摘要： A device includes a first and a second semiconductor-layer. The second semiconductor-layer is on the first semiconductor-layer, and has a first and a second side-surface. A first gate-dielectric is on the first semiconductor-layer. A second gate-dielectric is on the first side-surface. A gate has a bottom surface facing the first semiconductor-layer, and a third side-surface facing the first side-surface. A first diffusion-layer of a first conductivity-type is in a region in the second semiconductor-layer on a side of the second side-surface, and forms a junction with a region in the second semiconductor-layer on a side of the first side-surface. A silicide is on the second side-surface. A source of the first conductivity-type is in the first semiconductor-layer on a side of the third side-surface. A drain layer of a second conductivity-type is in the first semiconductor-layer on a side of a fourth side-surface of the gate electrode.
摘要翻译：一种器件包括第一和第二半导体层。第二半导体层位于第一半导体层上，并且具有第一和第二侧表面。第一栅电介质位于第一半导体层上。第二栅电介质位于第一侧表面上。栅极具有面向第一半导体层的底表面和面向第一侧表面的第三侧表面。第一导电型的第一扩散层位于第二半导体层的第二侧面一侧的区域中，与第一半导体层的第一侧面的第二侧面的第二半导体层的与第一半导体层侧面。硅化物位于第二侧面。第一导电类型的源在第三侧面的一侧的第一半导体层中。第二导电类型的漏极层位于栅电极的第四侧面一侧的第一半导体层中。

2. 发明申请

US20150263167A1 MULTIGATE DUAL WORK FUNCTION DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：多功能双工作功能装置及其制造方法
公开(公告)号：US20150263167A1
公开(公告)日：2015-09-17
申请号：US14333108
申请日：2014-07-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toshitaka MIYATA
IPC分类号： H01L29/78 , H01L29/66 , H01L29/49 , H01L21/311 , H01L21/28 , H01L29/423 , H01L29/51
CPC分类号： H01L21/31111 , H01L21/28035 , H01L21/28052 , H01L21/28158 , H01L29/42364 , H01L29/42368 , H01L29/42376 , H01L29/4916 , H01L29/4933 , H01L29/4983 , H01L29/512 , H01L29/517 , H01L29/66484 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66598 , H01L29/7831 , H01L29/7833
摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, a first gate insulator film provided on the channel region, a second gate insulator film provided on the channel region to be adjacent to the first gate insulator film on the source region side of the first gate insulator film, a first gate electrode provided on the first gate insulator film, and a second gate electrode provided on the second gate insulator film. An electrical thickness of the second gate insulator film is less than an electrical thickness of the first gate insulator film. A portion of the first gate electrode is provided on the second gate insulator film. A work function of the second gate electrode is higher than a work function of the first gate electrode.
摘要翻译：根据一个实施例，半导体器件包括漏极区域，源极区域，沟道区域，设置在沟道区域上的第一栅极绝缘膜，设置在与第一栅极绝缘体相邻的沟道区上的第二栅极绝缘膜在第一栅极绝缘膜的源极侧的膜，设置在第一栅极绝缘膜上的第一栅极电极和设置在第二栅极绝缘膜上的第二栅电极。第二栅极绝缘膜的电气厚度小于第一栅极绝缘膜的电学厚度。第一栅电极的一部分设置在第二栅绝缘膜上。第二栅电极的功函数高于第一栅电极的功函数。

3. 发明申请

US20150076553A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150076553A1
公开(公告)日：2015-03-19
申请号：US14145141
申请日：2013-12-31
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiyuki KONDO , Masakazu GOTO , Shigeru KAWANAKA , Toshitaka MIYATA
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66977 , H01L29/165 , H01L29/66356 , H01L29/66659 , H01L29/7391 , H01L29/7833
摘要： A semiconductor device according to the present embodiment includes a semiconductor layer. A gate dielectric film is provided on a surface of the semiconductor layer. A gate electrode is provided on the semiconductor layer via the gate dielectric film. A drain layer of a first conductivity type is provided in a part of the semiconductor layer on a side of a first end of the gate electrode. A source layer of a second conductivity type is provided in a part of the semiconductor layer on a side of a second end of the gate electrode and below the gate electrode. The source layer has a substantially uniform impurity concentration at the part of the semiconductor layer below the gate electrode. Voltages of a same polarity are applied to the gate electrode and the drain layer.
摘要翻译：根据本实施例的半导体器件包括半导体层。在半导体层的表面上设置栅极电介质膜。栅电极经由栅极电介质膜设置在半导体层上。第一导电类型的漏极层设置在栅电极的第一端侧的半导体层的一部分中。第二导电类型的源极层设置在半导体层的位于栅电极的第二端的一侧并且位于栅电极下方的一部分。源极层在栅电极下方的半导体层的部分具有基本均匀的杂质浓度。对栅电极和漏极层施加相同极性的电压。

4. 发明申请

US20150060772A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150060772A1
公开(公告)日：2015-03-05
申请号：US14078172
申请日：2013-11-12
申请人： Kabushiki Kaisha Toshiba
发明人： Toshitaka MIYATA
IPC分类号： H01L29/66
CPC分类号： H01L29/7391 , H01L29/66356 , H01L29/785
摘要： According to one embodiment, the pair of semiconductor regions are provided respectively on a pair of side walls of the second semiconductor layer having the fin configuration to form tunnel junctions with the second semiconductor layer. The gate electrode is provided on two sides of the second semiconductor layer at the pair of side walls to oppose the tunnel junctions with the semiconductor regions interposed between the gate electrode and the tunnel junctions. The third semiconductor layer is separated from the second semiconductor layer and the semiconductor regions by the first semiconductor layer to be adjacent to the first semiconductor layer.
摘要翻译：根据一个实施例，一对半导体区域分别设置在具有鳍结构的第二半导体层的一对侧壁上，以与第二半导体层形成隧道结。栅电极设置在第二半导体层的一对侧壁的两侧，与设置在栅电极和隧道结之间的半导体区域的隧道结相对。第三半导体层通过第一半导体层与第二半导体层和半导体区域分离以与第一半导体层相邻。

5. 发明申请

US20140071742A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20140071742A1
公开(公告)日：2014-03-13
申请号：US13839194
申请日：2013-03-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toshitaka MIYATA , Jyunichi OZEKI
IPC分类号： H01L43/02 , G11C11/16
CPC分类号： H01L43/02 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/228 , H01L43/08
摘要： According to one embodiment, a semiconductor memory device comprises a magnetoresistive element including a memory layer having a variable magnetization direction and made of a material which changes from ferromagnetism to paramagnetism when a voltage is applied, a reference layer having an invariable magnetization direction, and a tunnel barrier layer formed between the memory layer and the reference layer, a first interconnection electrically connected to one terminal of the magnetoresistive element, and a second interconnection electrically connected to the other terminal of the magnetoresistive element, and a third interconnection electrically insulated from the magnetoresistive element.
摘要翻译：根据一个实施例，半导体存储器件包括磁阻元件，其包括具有可变磁化方向的存储层，并且由施加电压时从铁磁性变为顺磁性的材料制成，具有不变磁化方向的参考层，以及形成在存储层和参考层之间的隧道势垒层，电连接到磁阻元件的一个端子的第一互连以及电连接到磁阻元件的另一个端子的第二互连，以及与磁阻电绝缘的第三互连元件。

6. 发明申请

US20140054657A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140054657A1
公开(公告)日：2014-02-27
申请号：US13766566
申请日：2013-02-13
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Akira HOKAZONO , Yoshiyuki KONDO , Toshitaka MIYATA
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L29/0843 , H01L29/1025 , H01L29/66356 , H01L29/66477 , H01L29/7391
摘要： In one embodiment, a semiconductor device includes a substrate, a gate insulator on the substrate, and a gate electrode on the gate insulator. The device further includes a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type disposed on a surface of the substrate so as to sandwich the gate electrode. The device further includes a junction forming region disposed between the source diffusion layer and the drain diffusion layer so as to contact the source diffusion layer. The junction forming region includes a source extension layer of the first conductivity type, a pocket layer of the second conductivity type above the source extension layer, and a diffusion suppressing layer disposed between the source extension layer and the pocket layer and containing carbon so as to suppress diffusion of impurities between the source extension layer and the pocket layer.
摘要翻译：在一个实施例中，半导体器件包括衬底，衬底上的栅极绝缘体和栅极绝缘体上的栅电极。该器件还包括第一导电类型的源极扩散层和第二导电类型的漏极扩散层，设置在衬底的表面上以夹着栅电极。该器件还包括设置在源极扩散层和漏极扩散层之间以便与源极扩散层接触的结形成区域。结形成区域包括第一导电类型的源极延伸层，在源延伸层上方的第二导电类型的袋层，以及设置在源延伸层和袋层之间并且含有碳的扩散抑制层，以便抑制杂质在源延伸层和袋层之间的扩散。

7. 发明申请

US20140175553A1 MOS SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译： MOS半导体器件及其制造方法
公开(公告)号：US20140175553A1
公开(公告)日：2014-06-26
申请号：US13901454
申请日：2013-05-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toshitaka MIYATA , Masakazu GOTO , Akira HOKAZONO
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7831 , H01L21/28105 , H01L21/28114 , H01L21/28132 , H01L29/42376 , H01L29/4983 , H01L29/512 , H01L29/517 , H01L29/66484 , H01L29/665 , H01L29/6656
摘要： According to one embodiment, a MOS semiconductor device comprises a first gate insulating film formed on a region of part of a channel of a semiconductor substrate, in which a transistor is to be formed, a first gate electrode formed on the first gate insulating film, a second gate insulating film formed on remaining part of the channel, the second gate insulating film including an impurity added to the second gate insulating film to increase a threshold value of the channel immediately under the second gate insulating film, and a second gate electrode formed on the second gate insulating film.
摘要翻译：根据一个实施例，一种MOS半导体器件包括：第一栅极绝缘膜，形成在要形成晶体管的半导体衬底的沟道的一部分的区域上，形成在第一栅极绝缘膜上的第一栅电极，形成在所述沟道的剩余部分上的第二栅极绝缘膜，所述第二栅极绝缘膜包括添加到所述第二栅极绝缘膜上的杂质以增加所述第二栅极绝缘膜正下方的沟道的阈值，以及形成的第二栅极在第二栅绝缘膜上。

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