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1. 发明申请

US20180261504A1 FDSOI WITH ON-CHIP PHYSICALLY UNCLONABLE FUNCTION 审中-公开
公开(公告)号：US20180261504A1
公开(公告)日：2018-09-13
申请号：US15978508
申请日：2018-05-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
IPC分类号： H01L21/768 , H01L29/78 , H01L27/12 , H01L27/112 , G06F21/44 , H01L21/84 , H01L23/00
CPC分类号： H01L21/76877 , G06F21/44 , G06F21/73 , G09C1/00 , H01L21/84 , H01L23/544 , H01L23/57 , H01L27/11233 , H01L27/1203 , H01L29/7838 , H01L2223/5444 , H04L9/3278
摘要： An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.

2. 发明授权

US09916903B2 OTPROM for post-process programming using selective breakdown 有权
公开(公告)号：US09916903B2
公开(公告)日：2018-03-13
申请号：US14514289
申请日：2014-10-14
申请人： GlobalFoundries Inc.
发明人： Akhilesh Gautam , Suresh Uppal , Min-hwa Chi
IPC分类号： G11C17/12 , H01L27/112 , G11C17/18
CPC分类号： G11C17/12 , G11C17/18 , H01L27/11233
摘要： At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

3. 发明授权

US08664706B2 Current in one-time-programmable memory cells 有权
标题翻译：一次可编程存储单元中的电流
公开(公告)号：US08664706B2
公开(公告)日：2014-03-04
申请号：US13528250
申请日：2012-06-20
申请人： Shanjen “Robert” Pan , Allan T. Mitchell , Weidong Tian
发明人： Shanjen “Robert” Pan , Allan T. Mitchell , Weidong Tian
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L21/28273 , H01L27/11206 , H01L27/11233 , H01L29/66825 , H01L29/7885
摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.
摘要翻译：一种在其编程状态之一制造具有改进的读取电流的一次可编程（OTP）存储单元的方法，以及如此制造的存储单元。 OTP存储单元的侧面由沟槽隔离结构构成。在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。植入物可能垂直于装置表面或与法线成一角度。然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。来自氟植入物的改进的导通电流（Ion）。

4. 发明授权

US07164294B2 Method for forming programmable logic arrays using vertical gate transistors 失效
标题翻译：使用垂直栅极晶体管形成可编程逻辑阵列的方法
公开(公告)号：US07164294B2
公开(公告)日：2007-01-16
申请号：US10929831
申请日：2004-08-30
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： G11C8/00 , H03K19/084 , G06F7/38 , H01L29/76
CPC分类号： H01L27/112 , H01L27/11233 , H01L27/11803 , H01L29/42324 , H01L29/42368 , H01L29/66484 , H01L29/7831
摘要： One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical function. Forming the logic cells includes forming a horizontal substrate with a source region, a drain region, and a depletion mode channel region separating the source and the drain regions, and further includes forming a number of vertical gates located above different portions of the depletion mode channel region. At least one vertical gate is separated from the depletion mode channel region by a first oxide thickness, and at least one of the vertical gates is separated from the depletion mode channel region by a second oxide thickness. Other aspects and embodiments are provided herein.
摘要翻译：本文公开的一个方面涉及一种用于形成可编程逻辑阵列的方法。该方法的各种实施例包括形成第一逻辑平面和第二逻辑平面，每个逻辑平面和第二逻辑平面包括互连的多个逻辑单元以实现逻辑功能。形成逻辑单元包括：形成具有分离源极区和漏极区的源极区，漏极区和耗尽模式沟道区的水平衬底，并且还包括形成位于耗尽模式沟道的不同部分上方的多个垂直栅极地区。至少一个垂直栅极与耗尽模式沟道区分离第一氧化物厚度，并且至少一个垂直栅极与耗尽模式沟道区分离第二氧化物厚度。本文提供了其它方面和实施例。

5. 发明授权

US06955966B2 Method of manufacturing non-volatile read only memory 失效
标题翻译：制造非易失性只读存储器的方法
公开(公告)号：US06955966B2
公开(公告)日：2005-10-18
申请号：US10895382
申请日：2004-07-21
申请人： Noboru Egawa , Hitoshi Kokubun
发明人： Noboru Egawa , Hitoshi Kokubun
IPC分类号： G11C11/56 , G11C17/12 , H01L21/8246 , H01L27/112 , H01L21/336
CPC分类号： H01L27/11266 , G11C11/5692 , G11C17/126 , H01L27/112 , H01L27/11233
摘要： A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas in accordance with quaternary write data. A current runs between these diffusion areas only when one of these two areas which is adjacent a gap is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.
摘要翻译：制造用于存储四元数据的掩模ROM的方法能够实现短周转时间，使精细单元尺寸简单，并且能够稳定地读取数据。根据四次写入数据，在存储单元晶体管中的字线和两个扩散区域之间形成间隙。只有当这两个邻近间隙的区域中的一个被用作漏极时，电流在这些扩散区域之间运行。因此，当第一扩散区域是源极并且另一个扩散区域是漏极时，可以通过第一读取读取四元数据，并且当第一扩散区域用作漏极时读取第二读数，而另一个扩散区域作为来源。

6. 发明申请

US20020191432A1 Read-only MOS memory 失效
标题翻译：只读MOS存储器
公开(公告)号：US20020191432A1
公开(公告)日：2002-12-19
申请号：US10172179
申请日：2002-06-14
申请人： STMicroelectronics S.A.
发明人： Sigrid Thomas
IPC分类号： G11C005/06
CPC分类号： H01L27/11233 , G11C17/12 , H01L27/112
摘要： A read-only memory formed of cells, each of which includes, between a selection line and a bit line, the series connection of a memory element and of a selection MOS transistor with a gate connected to a read control line. The memory elements of blank cells are P-channel MOS transistors and the memory elements of programmed cells are uniformly N-type doped semiconductor regions.
摘要翻译：由单元形成的只读存储器，每个单元在选择线和位线之间包括存储元件和选择MOS晶体管的串联连接，栅极连接到读控制线。空白单元的存储元件是P沟道MOS晶体管，并且编程单元的存储元件是均匀的N型掺杂半导体区域。

7. 发明授权

US06211014B1 Three-dimensional, deep-trench, high-density read-only memory (ROM) and its manufacturing method 失效
标题翻译：三维，深沟，高密度只读存储器（ROM）及其制造方法
公开(公告)号：US06211014B1
公开(公告)日：2001-04-03
申请号：US09059417
申请日：1998-04-14
申请人： Chen-Chung Hsu
发明人： Chen-Chung Hsu
IPC分类号： H01L21336
CPC分类号： H01L27/11233
摘要： A three-dimensional, deep-trench, high-density ROM and its manufacturing method are provided. The ROM device comprises a silicon substrate having a plurality of parallel trenches above it surface, wherein, between every two adjacent trenches, there is a higher region. During programming of the ROM device, deeper trenches are formed to define the OFF-state non-conducting memory cells, so that misalignment problems that lead to transistor cell leakage are prevented. The ROM device provides reduced breakdown of the source/drain regions as well.
摘要翻译：提供三维，深沟，高密度ROM及其制造方法。 ROM器件包括在其表面上方具有多个平行沟槽的硅衬底，其中在每两个相邻的沟槽之间存在较高的区域。在ROM器件的编程期间，形成更深的沟槽以限定非导通状态的非导通存储器单元，从而防止导致晶体管单元泄漏的未对准问题。 ROM器件还提供了源极/漏极区域的降低的击穿。

8. 发明申请

US20170263575A1 FDSOI WITH ON-CHIP PHYSICALLY UNCLONABLE FUNCTION 有权
公开(公告)号：US20170263575A1
公开(公告)日：2017-09-14
申请号：US15063644
申请日：2016-03-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
IPC分类号： H01L23/00 , H01L29/78 , H01L21/768 , H01L27/02 , H01L21/84 , G06F21/44 , H01L27/12
CPC分类号： H01L21/76877 , G06F21/44 , G06F21/73 , G09C1/00 , H01L21/76816 , H01L21/84 , H01L23/544 , H01L23/57 , H01L27/11233 , H01L27/1203 , H01L29/7838 , H01L2223/5444 , H04L9/3278
摘要： An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the devices. The logic pattern is determined in accordance with processing variations during manufacture of the array. The logic pattern is represented with a first state for one or more devices with contact shorts and a second state with one or more devices without contact shorts.

9. 发明授权

US09659944B2 One time programmable memory with a twin gate structure 有权
公开(公告)号：US09659944B2
公开(公告)日：2017-05-23
申请号：US14871792
申请日：2015-09-30
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Qintao Zhang , Mei Xue , Wenwei Yang , Akira Ito
IPC分类号： H01L27/112 , G11C17/16 , G11C17/18
CPC分类号： H01L27/11233 , G11C17/16 , G11C17/18 , H01L27/11206
摘要： A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL.

10. 发明申请

US20170005103A1 One Time Programmable Memory with a Twin Gate Structure 有权
标题翻译：具有双门结构的一次性可编程存储器
公开(公告)号：US20170005103A1
公开(公告)日：2017-01-05
申请号：US14871792
申请日：2015-09-30
申请人： Broadcom Corporation
发明人： Qintao ZHANG , Mei XUE , Wenwei YANG , Akira ITO
IPC分类号： H01L27/112 , G11C17/18 , G11C17/16
CPC分类号： H01L27/11233 , G11C17/16 , G11C17/18 , H01L27/11206
摘要： A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL.
摘要翻译：提供了包括组合字线编程线（WL-PL）的一次性可编程存储器（OTP）。 OTP包括具有第一阈值电压和第一击穿电压的可编程晶体管，以及具有第二阈值电压和第二击穿电压的通过晶体管。组合的WL-PL电连接到可编程晶体管和传输晶体管的相应栅电极，使得两者都接收相同的控制电压。第二栅电极具有大于第一栅极电极的功函数，使得第二栅极击穿电压大于第一栅极击穿电压，这使得能够使用组合的WL-PL。

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