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1. 发明申请

US20170005093A1 Semiconductor Device with Split Work Functions 审中-公开
标题翻译：具有分离功能的半导体器件
公开(公告)号：US20170005093A1
公开(公告)日：2017-01-05
申请号：US14788215
申请日：2015-06-30
申请人： Broadcom Corporation
发明人： Qintao ZHANG , Mei XUE , Wenwei YANG , Akira ITO
IPC分类号： H01L27/092 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/42372 , H01L29/4966 , H01L29/4983 , H01L29/7833 , H01L29/7835
摘要： A field effect transistor (FET) configuration is provided having a gate region with a split work function for the source-side and drain-side of the gate region. The work function of a material is defined as the minimum energy required to extract an electron from the surface of the material to free space. Accordingly, the source-side portion of the gate region has a first work function that less than a second work function of the drain-side portion, the result of which is increased breakdown voltage at the drain-gate interface, without significantly increasing the threshold voltage of the FET. The split work function is achieved by layering n-type gate material over p-type gate material in the drain-side portion of the gate region, while only the n-type gate material us used in the source-side portion of the gate region.
摘要翻译：提供场效应晶体管（FET）构造，其具有栅极区域，该栅极区域具有用于栅极区域的源极侧和漏极侧的分离功能。材料的功函数定义为将电子从材料表面提取到自由空间所需的最小能量。因此，栅极区域的源侧部分具有小于漏极侧部分的第二功函数的第一功函数，其结果是增加了漏极 - 栅极界面处的击穿电压，而不显着增加阈值 FET的电压。通过在栅极区域的漏极侧部分中的p型栅极材料上层叠n型栅极材料，而在栅极区域的源极侧仅使用n型栅极材料来实现分裂功函数。

2. 发明申请

US20160181358A1 SUPER JUNCTION LDMOS FINFET DEVICES 有权
标题翻译：超级连接LDMOS FINFET器件
公开(公告)号：US20160181358A1
公开(公告)日：2016-06-23
申请号：US14598119
申请日：2015-01-15
申请人： BROADCOM CORPORATION
发明人： Qintao ZHANG , Akira ITO
IPC分类号： H01L29/06 , H01L29/49 , H01L29/40 , H01L29/78 , H01L29/66
CPC分类号： H01L29/0634 , H01L29/063 , H01L29/0847 , H01L29/0865 , H01L29/0882 , H01L29/165 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66681 , H01L29/66689 , H01L29/6681 , H01L29/7823 , H01L29/7835 , H01L29/785 , H01L29/7851 , H01L29/7855
摘要： A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a top surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the top surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the top surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant.
摘要翻译：提供了一种鳍状场效应晶体管（finFET）器件。 finFET器件包括具有顶表面和底表面的衬底材料。 finFET器件还包括形成在衬底材料中的阱区。阱区可以包括第一类型的掺杂剂。 finFET器件还包括设置在衬底材料的顶表面上的翅片结构。翅片结构的一部分可以包括第一类型的掺杂剂。 finFET器件还包括设置在衬底材料的顶表面上并且与鳍结构的部分相邻的氧化物材料。 finFET器件还包括设置在鳍结构的一部分上的第一外延材料。第一外延材料可以包括第二类型的掺杂剂。

3. 发明申请

US20160071935A1 NATIVE PMOS DEVICE WITH LOW THRESHOLD VOLTAGE AND HIGH DRIVE CURRENT AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有低阈值电压和高驱动电流的本底PMOS器件及其制造方法
公开(公告)号：US20160071935A1
公开(公告)日：2016-03-10
申请号：US14935967
申请日：2015-11-09
申请人： Broadcom Corporation
发明人： Akira ITO
IPC分类号： H01L29/10 , H01L29/08 , H01L29/51 , H01L29/78 , H01L29/49 , H01L29/165 , H01L29/06
CPC分类号： H01L29/1083 , H01L21/28123 , H01L21/76224 , H01L21/823456 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/165 , H01L29/495 , H01L29/4958 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7833 , H01L29/7848
摘要： A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.
摘要翻译：在本公开中讨论了在短沟道长度的变化范围内呈现低阈值电压和高驱动电流的天然p型金属氧化物半导体（PMOS）器件及其制造方法。天然PMOS器件的源极和漏极区域各自包括应变区域，重掺杂凸起区域和轻掺杂区域。栅极区域包括具有高k介电材料，金属和接触金属的栅极氧化物的堆叠层。天然PMOS器件的高驱动电流主要受到由于应变区域增加的载流子迁移率的影响，由于升高的区域引起的较低的漏极电阻以及由于天然PMOS的高k栅极氧化物导致的较高的栅极电容设备。

4. 发明申请

US20150108557A1 METAL-INSULATOR-METAL CAPACITOR STRUCTURE 有权
标题翻译：金属绝缘体 - 金属电容器结构
公开(公告)号：US20150108557A1
公开(公告)日：2015-04-23
申请号：US14072723
申请日：2013-11-05
申请人： Broadcom Corporation
发明人： Shom Surendran PONOTH , Changyok PARK , Guang-Jye SHIAU , Akira ITO
IPC分类号： H01L27/08 , H01L49/02
CPC分类号： H01L27/0629 , H01L23/5223 , H01L27/0805 , H01L27/10855 , H01L28/40 , H01L28/60 , H01L28/90 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.
摘要翻译：半导体器件中的电容器结构包括具有顶表面和与顶表面相对的底表面的半导体衬底，隔离区域具有与顶表面相对的顶表面和底表面，隔离区域的底表面设置在半导体衬底的顶表面上。电容器结构还包括设置在隔离区域的顶表面上的栅极端子结构和设置在隔离区域的顶表面上且平行于栅极端子结构设置的扩散接触结构。在一些方面，栅极端子结构连接到第一接触节点，并且扩散接触结构连接到第二接触节点，其中第一和第二接触节点形成电容器结构的相对节点。

5. 发明申请

US20170005103A1 One Time Programmable Memory with a Twin Gate Structure 有权
标题翻译：具有双门结构的一次性可编程存储器
公开(公告)号：US20170005103A1
公开(公告)日：2017-01-05
申请号：US14871792
申请日：2015-09-30
申请人： Broadcom Corporation
发明人： Qintao ZHANG , Mei XUE , Wenwei YANG , Akira ITO
IPC分类号： H01L27/112 , G11C17/18 , G11C17/16
CPC分类号： H01L27/11233 , G11C17/16 , G11C17/18 , H01L27/11206
摘要： A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL.
摘要翻译：提供了包括组合字线编程线（WL-PL）的一次性可编程存储器（OTP）。 OTP包括具有第一阈值电压和第一击穿电压的可编程晶体管，以及具有第二阈值电压和第二击穿电压的通过晶体管。组合的WL-PL电连接到可编程晶体管和传输晶体管的相应栅电极，使得两者都接收相同的控制电压。第二栅电极具有大于第一栅极电极的功函数，使得第二栅极击穿电压大于第一栅极击穿电压，这使得能够使用组合的WL-PL。

6. 发明申请

US20140312396A1 SPLIT MULTI-GATE FIELD-EFFECT TRANSISTOR 有权
标题翻译：分离多栅极场效应晶体管
公开(公告)号：US20140312396A1
公开(公告)日：2014-10-23
申请号：US13898414
申请日：2013-05-20
申请人： Broadcom Corporation
发明人： Akira ITO
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/7856
摘要： A semiconductor device based on split multi-gate field-effect transistor radio frequency devices is provided. The semiconductor device includes a substrate and a gate structure above the substrate and orthogonal to a channel axis. The semiconductor device also includes a semiconductor fin structure above the substrate along the channel axis. The semiconductor also includes a gate oxide region beneath the gate structure and in contact with the gate structure and the semiconductor fin structure. The gate oxide region has a first region with a first thickness and a first length. The gate oxide region also has a second region with a second thickness and a second length. The first thickness is greater than the second thickness. The first region and the second region are formed side-by-side along the channel axis.
摘要翻译：提供了一种基于分离多栅极场效应晶体管射频器件的半导体器件。半导体器件包括衬底和位于衬底上方并与通道轴线正交的栅极结构。半导体器件还包括沿着沟道轴线在衬底上方的半导体鳍结构。半导体还包括栅极结构下方的栅极氧化物区域，并与栅极结构和半导体鳍片结构接触。栅极氧化物区域具有第一厚度和第一长度的第一区域。栅极氧化物区域还具有第二厚度和第二长度的第二区域。第一厚度大于第二厚度。第一区域和第二区域沿通道轴线并排地形成。

7. 发明申请

US20140197497A1 NATIVE PMOS DEVICE WITH LOW THRESHOLD VOLTAGE AND HIGH DRIVE CURRENT AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有低阈值电压和高驱动电流的本底PMOS器件及其制造方法
公开(公告)号：US20140197497A1
公开(公告)日：2014-07-17
申请号：US13741157
申请日：2013-01-14
申请人： BROADCOM CORPORATION
发明人： Akira ITO
IPC分类号： H01L29/78
CPC分类号： H01L29/1083 , H01L21/28123 , H01L21/76224 , H01L21/823456 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/165 , H01L29/495 , H01L29/4958 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7833 , H01L29/7848
摘要： A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.
摘要翻译：在本公开中讨论了在短沟道长度的变化范围内呈现低阈值电压和高驱动电流的天然p型金属氧化物半导体（PMOS）器件及其制造方法。天然PMOS器件的源极和漏极区域各自包括应变区域，重掺杂凸起区域和轻掺杂区域。栅极区域包括具有高k介电材料，金属和接触金属的栅极氧化物的堆叠层。天然PMOS器件的高驱动电流主要受到由于应变区域增加的载流子迁移率的影响，由于升高的区域引起的较低的漏极电阻以及由于天然PMOS的高k栅极氧化物导致的较高的栅极电容设备。

8. 发明申请

US20170018612A1 SPLIT-GATE DEVICES 审中-公开
标题翻译：分闸装置
公开(公告)号：US20170018612A1
公开(公告)日：2017-01-19
申请号：US14820444
申请日：2015-08-06
申请人： BROADCOM CORPORATION
发明人： Akira ITO
IPC分类号： H01L29/10 , H01L21/283 , H01L29/08 , H01L21/225 , H01L29/78 , H01L29/06
CPC分类号： H01L29/1095 , H01L21/2253 , H01L21/2254 , H01L21/283 , H01L21/823462 , H01L27/088 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1045 , H01L29/1083 , H01L29/42368 , H01L29/7816 , H01L29/7833
摘要： A semiconductor device includes a substrate having a source region and a drain region implanted with a second dopant by a second ion implantation. The substrate includes a first well region implanted with a first dopant by a first ion implantation and a second well region blocked from the first ion implantation forming a native section. The drain region is within the native section and the source region is within the first well region. The device includes a gate dielectric layer having a first region with a thickness different from that of a second region of the gate dielectric layer. The first region of the gate dielectric layer is located above the first well region and the second region of the gate dielectric layer is located above the second well region. The device includes a gate electrode disposed on the gate dielectric layer forming a gate structure on the substrate.
摘要翻译：半导体器件包括具有通过第二离子注入而注入了第二掺杂剂的源区和漏区的衬底。衬底包括通过第一离子注入注入第一掺杂剂的第一阱区域和阻挡第一离子注入的第二阱区域，形成天然区段。漏极区域在原始区域内，源极区域在第一阱区域内。该器件包括具有与栅极电介质层的第二区域的厚度不同的厚度的第一区域的栅极介电层。栅极电介质层的第一区域位于第一阱区域的上方，栅极电介质层的第二区域位于第二阱区域的上方。该器件包括设置在栅极电介质层上的栅电极，在该衬底上形成栅极结构。

9. 发明申请

US20160149033A1 INCREASING BREAKDOWN VOLTAGE OF LDMOS DEVICES FOR FOUNDRY PROCESSES 审中-公开
标题翻译：增加破碎过程的LDMOS器件的断开电压
公开(公告)号：US20160149033A1
公开(公告)日：2016-05-26
申请号：US14562654
申请日：2014-12-05
申请人： BROADCOM CORPORATION
发明人： Akira ITO
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L21/265 , H01L21/266 , H01L27/06 , H01L29/08 , H01L29/66
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/266 , H01L29/0653 , H01L29/0878 , H01L29/66689
摘要： A laterally defused MOS (LDMOS) device with improved breakdown voltage includes a substrate including a deep well, a drain region formed in the deep well and in contact with a first region of the deep well, and a source region formed in the deep well and in contact with a second region of the deep well. The doping concentrations of the first and second regions of the deep well are different from one another. A difference between the doping concentrations of the first and second regions of the deep well depends on an implant layout technique used to form the deep well.
摘要翻译：具有改进的击穿电压的侧向消除的MOS（LDMOS）器件包括：衬底，其包括深阱，形成在深阱中并与深阱的第一区接触的漏极区，以及形成在深阱中的源极区，与深井的第二区域接触。深井的第一和第二区域的掺杂浓度彼此不同。深井的第一和第二区域的掺杂浓度之间的差异取决于用于形成深井的植入物布局技术。

10. 发明申请

US20150333066A1 FIELD EFFECT TRANSISTOR STRUCTURE HAVING ONE OR MORE FINS 审中-公开
标题翻译：具有一个或多个FINS的场效应晶体管结构
公开(公告)号：US20150333066A1
公开(公告)日：2015-11-19
申请号：US14810269
申请日：2015-07-27
申请人： Broadcom Corporation
发明人： Akira ITO
IPC分类号： H01L27/092 , H01L29/10 , H01L29/16 , H01L29/06
CPC分类号： H01L27/0924 , H01L29/0653 , H01L29/1079 , H01L29/16 , H01L29/66795 , H01L29/7835 , H01L29/785 , H01L29/7851
摘要： A field effect transistor (FET) having one or more fins provides an extended current path as compared to conventional finFETs. A raised source terminal is disposed on a fin adjacent to a sidewall spacer of a gate structure. The drain terminal and a first portion of the gate structure overlie a first well of a first conductivity type. A raised drain terminal is disposed such that it is spaced apart from the gate structure sidewalls. In some embodiments the drain terminal is disposed on a second, separate fin. The drain terminal and a second portion of the gate structure overlie a second well of a second conductivity type.
摘要翻译：具有一个或多个鳍片的场效应晶体管（FET）与传统的鳍状FET相比提供了扩展的电流路径。凸起的源极端子设置在与栅极结构的侧壁间隔物相邻的翅片上。漏极端子和栅极结构的第一部分覆盖第一导电类型的第一阱。升高的漏极端子被设置成使其与栅极结构侧壁间隔开。在一些实施例中，漏极端子设置在第二分开的鳍片上。漏极端子和栅极结构的第二部分覆盖第二导电类型的第二阱。

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