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1. 发明申请

US20190213152A1 SOFTWARE-DEFINED DEVICE INTERFACE SYSTEM AND METHOD 审中-公开
公开(公告)号：US20190213152A1
公开(公告)日：2019-07-11
申请号：US16330677
申请日：2017-09-05
申请人： IoT.nxt (PTY) LTD
发明人： Gysbert Johannes Jacobs , Rudi Deodat Du Toit
IPC分类号： G06F13/20 , G06F1/08 , G06F15/78 , G06F13/42
CPC分类号： G06F13/20 , G06F1/08 , G06F3/038 , G06F5/16 , G06F13/42 , G06F15/00 , G06F15/7817 , G06F21/76 , G06F21/85 , G06F2213/40 , H04L67/12 , H04L67/34 , H04L69/18
摘要： The invention relates to a software defined device interface system 10, a software defined device interface, gateway and a method of defining an interface for a device which uses a specific communication protocol for communication purposes. The system 10 includes a microprocessor/processing unit 12.1, 12.2 with a plurality of communication pins and software/firmware. The software/firmware is configured, based on a specific communication protocol which is used by a particular device 30.1-30.4 for communication purposes, to, in runtime, assign/select one or more of the communication pins to form a virtual port to which the particular device 30.1-30.4 can be connected, upon receiving a configuration instruction from a user to implement the specific communication protocol. The software/firmware is further configured to implement the specific communication protocol through the virtual port, to thereby allow for communication between the microprocessor/processing unit 12.1, 12.2 and the device 30.1-30.4, when the device 30.1-30.4 is connected to the pin(s) of the virtual port.

2. 发明申请

US20170322769A1 FIXED-POINT AND FLOATING-POINT ARITHMETIC OPERATOR CIRCUITS IN SPECIALIZED PROCESSING BLOCKS 审中-公开
公开(公告)号：US20170322769A1
公开(公告)日：2017-11-09
申请号：US15451467
申请日：2017-03-07
申请人： Altera Corporation
发明人： Martin Langhammer
IPC分类号： G06F7/485 , G06F5/16 , G06F5/01
CPC分类号： G06F7/485 , G06F5/012 , G06F5/16 , G06F7/483 , G06F7/505 , G06F2207/3824
摘要： The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion thereof, a fixed-point or floating-point multiplication operation or a portion thereof, a fixed-point or floating-point multiply-add operation or a portion thereof, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floating-point numbers or a Radix-2 Butterfly circuit, just to name a few.

3. 发明授权

US09459829B2 Low latency first-in-first-out (FIFO) buffer 有权
标题翻译：低延迟先进先出（FIFO）缓冲区
公开(公告)号：US09459829B2
公开(公告)日：2016-10-04
申请号：US14331882
申请日：2014-07-15
申请人： Marvell Israel (M.I.S.L.) Ltd.
发明人： Evgeny Shumsky , Jonathan Kushnir
IPC分类号： G06F5/00 , G06F5/12 , G06F5/14 , G06F5/16 , G06F5/06
CPC分类号： G06F5/12 , G06F5/065 , G06F5/14 , G06F5/16 , G06F2205/065 , G06F2205/126
摘要： Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.
摘要翻译：为先进先出缓冲区提供系统和方法。缓冲器包括被配置为存储从缓冲器输入接收的数据的第一子缓冲器和第二子缓冲器。第二子缓冲器被配置为存储从缓冲器输入或第一子缓冲器接收的数据，并以与在缓冲器输入处接收的数据相同的顺序将数据输出到缓冲器输出。缓冲器控制逻辑被配置为选择性地将数据从缓冲器输入或第一子缓冲器路由到第二子缓冲器，使得在缓冲器输入处接收到的数据可用于以第一子缓冲器的方式从第二子缓冲器输出，先到先得。

4. 发明申请

US20160246570A1 LINE-MULTIPLEXED UART 有权
标题翻译：线路多路复用UART
公开(公告)号：US20160246570A1
公开(公告)日：2016-08-25
申请号：US14631078
申请日：2015-02-25
申请人： QUALCOMM Incorporated
发明人： Lalan Jee Mishra , Richard Dominic Wietfeldt , George Alan Wiley
IPC分类号： G06F5/16 , G06F5/06 , G06F1/12 , G06F13/40 , G06F13/16
CPC分类号： G06F5/16 , G06F1/12 , G06F5/065 , G06F13/1673 , G06F13/385 , G06F13/4022
摘要： A line multiplexed UART interface is provided that multiplexes a UART transmit and CTS functions on a transmit pin and that multiplexes a UART receive and RTS functions on a receive pin. In this fashion, the conventional need for an additional RTS pin and an additional CTS pin is obviated such that the line multiplexed UART interface uses just the transmit pin and the receive pin.
摘要翻译：提供了一种线路复用UART接口，可在发送引脚上复用UART发送和CTS功能，并在接收引脚上复用UART接收和RTS功能。以这种方式，消除了额外的RTS引脚和附加CTS引脚的常规需求，使得线路复用UART接口仅使用发送引脚和接收引脚。

5. 发明授权

US09383967B2 Accumulation of waveform data using alternating memory banks 有权
标题翻译：使用交替记忆库累积波形数据
公开(公告)号：US09383967B2
公开(公告)日：2016-07-05
申请号：US14026167
申请日：2013-09-13
申请人： NATIONAL INSTRUMENTS CORPORATION
发明人： Anita L. Salmon , Jeff A. Bergeron , Andrew C. Thomson
IPC分类号： H03M1/12 , G06F5/06 , G06F13/16 , G06F13/28 , G06F5/16
CPC分类号： G06F5/065 , G06F5/16 , G06F13/1647 , G06F13/28
摘要： System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.
摘要翻译：用于硬件实现的波形数据累积的系统和方法。提供数字转换器，其包括：电路，以及耦合到该电路的第一和第二存储体。电路可以被配置为：将波形的第一子集存储在第一存储体中，以块方式累积每个波形，其中每个块具有指定的大小，从而产生第一组合和，其包括第一部分积累所述波形集合与所述累积同时存储在所述第二存储体中的波形的第二子集，并且以块方式累积所述第二波形子集的每个波形，从而生成包括第二部分累积的第二部分积分波形组，其中该组波形的第一和第二部分累积可用于生成该组波形的累积记录。

6. 发明授权

US09239702B2 Data processing apparatus 有权
标题翻译：数据处理装置
公开(公告)号：US09239702B2
公开(公告)日：2016-01-19
申请号：US11570167
申请日：2005-06-08
申请人： Antonius Adrianus Maria Van Wel
发明人： Antonius Adrianus Maria Van Wel
IPC分类号： G06F5/01 , G06F5/00 , G06F7/76 , G06F9/30 , H04N19/184 , H04N19/169 , H04N19/42 , H04N19/436 , H04B1/66 , G06F5/16
CPC分类号： G06F5/01 , G06F5/00 , G06F5/015 , G06F5/16 , G06F7/76 , G06F7/762 , G06F7/768 , G06F9/30018 , G06F9/30029 , G06F9/30036 , H04B1/66 , H04B1/667 , H04N19/184 , H04N19/1883 , H04N19/42 , H04N19/436
摘要： A programmable data processing apparatus having a bit-plane extraction operation is described, for extracting data from a value of, for example, 32 bits containing 4 bytes, 1a to 1d. Each byte 1a to 1d comprises 8 bits, (a0-a7, b0-b7, c0-c7 and d0-d7, respectively). The bit-plane extraction operation retrieves one bit from each of these bytes, for example the second bit (a1, b1, c1, d1), which is specified by an argument. The operation involves concatenating these bits (a1, b1, c1, d1) and returning a result value 5. Depending on the particular data processing application, the result value may be bit-reversed to provide a result value 7 (for example, if a bit-reversal is required to deal with endianness, or other reasons). The bit-plane extraction operation can be used as a pre-processing operation in data processing operations such as “sum-of-absolute-differences” in the processing of video data.
摘要翻译：描述了具有位平面提取操作的可编程数据处理装置，用于从例如包含4字节的数据的1a，1d到1d的值提取数据。每个字节1a至1d包括8位（分别为a0-a7，b0-b7，c0-c7和d0-d7）。位平面提取操作从这些字节中的每一个中检索一位，例如由参数指定的第二位（a1，b1，c1，d1）。该操作涉及连接这些位（a1，b1，c1，d1）并返回结果值5.根据特定的数据处理应用，结果值可以被比特反转以提供结果值7（例如，如果a 需要位反转以处理字节或其他原因）。位图提取操作可以用作数据处理操作中的预处理操作，诸如视频数据处理中的“绝对差之和”。

7. 发明授权

US09229683B2 Communication device ingress information management system and method 有权
公开(公告)号：US09229683B2
公开(公告)日：2016-01-05
申请号：US14570083
申请日：2014-12-15
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： Graeme McKerrell , Peter Saunderson
IPC分类号： G06F13/12 , H04L12/28 , G06F5/16 , H04L12/70 , H04L12/851 , H04L12/835
CPC分类号： H04L63/1458 , G06F5/16 , G06F2205/066 , H04L47/00 , H04L47/2441 , H04L47/30 , H04L49/90
摘要： The components of communication network device ingress systems and methods cooperate to manage information ingress and prevent denial of service attempts. A classifier classifies incoming information. A classification filter filters the information on a classification basis to prevent denial of service. The classification filter includes a classification filter counter for tracking the flow of information associated with the classification filter. A zero value in the classification filter counter indicates that a buffer capacity limit associated with the classification is reached. The counter permits information to flow to a packet buffer if the classification filter counter value is not zero and discards information if the classification filter counter value is zero. In one exemplary implementation the classification filter counter decrements a classification filter counter value when the information is placed in the buffer. The classification filter counter value is incremented when the information is processed out of the buffer.

8. 发明申请

US20150074160A1 S12 TX FIR ARCHITECTURE 审中-公开
公开(公告)号：US20150074160A1
公开(公告)日：2015-03-12
申请号：US14524774
申请日：2014-10-27
申请人： STMICROELECTRONICS (CANADA), INC. , STMICROELECTRONICS S.r.l.
发明人： JOHN HOGEBOOM , HOCK KHOR , MATTEO ALESSIO TRALDI , ANTON PELTESHKI
IPC分类号： G06F7/72 , G06F5/16
CPC分类号： G06F7/724 , G06F5/16 , H03H17/06 , H04L25/0272 , H04L25/0288
摘要： A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
摘要翻译： FIR发送架构使用多个驱动器分区，以允许具有不同延迟的信号被驱动器自身求和到输出信号中。该架构包括第一多路复用器，多个延迟单元，多个符号块，开关块，第二多路复用器和多个驱动器。

9. 发明申请

US20140210518A1 Resonant Inductor Coupling Clock Distribution 有权
标题翻译：谐振电感耦合时钟分布
公开(公告)号：US20140210518A1
公开(公告)日：2014-07-31
申请号：US13849115
申请日：2013-03-22
申请人： Broadcom Corporation
发明人： David CHANG , Ajat HUKKOO
IPC分类号： H03K19/096
CPC分类号： H03K19/096 , G06F1/00 , G06F1/10 , G06F1/266 , G06F1/3287 , G06F5/16 , H01F38/14 , H02J50/05 , H02J50/10
摘要： The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal.
摘要翻译：本公开提供了一种用于在同步顺序逻辑电路内分配时钟信号的时钟分配网络。时钟分配网络通过将时钟信号从主分配节点感应和/或电容耦合到同步顺序逻辑电路内的各个次分布节点来分配一个或多个时钟信号。各个次级分布节点在相应的谐振频率处谐振，以产生响应于接收时钟信号而在同步顺序逻辑电路内使用的其它时钟信号。

10. 发明授权

US08762602B2 Variable-length code (VLC) bitstream parsing in a multi-core processor with buffer overlap regions 有权
标题翻译：可变长度码（VLC）比特流在具有缓冲区重叠区域的多核处理器中解析
公开(公告)号：US08762602B2
公开(公告)日：2014-06-24
申请号：US12177232
申请日：2008-07-22
申请人： Kuan Feng , Huo Ding Li , Xing S H Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Kuan Feng , Huo Ding Li , Xing S H Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00 , H04N7/12 , H03M7/40
CPC分类号： G06F5/16
摘要： An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor may includes two SPU buffers. The processor first transfers bitstream data into GPU buffer memory and then populates the SPU buffers one after another with bitstream data. The SPU buffers may each include an overlap region that the SPU populates with the same bitstream data. The SPU parses the bitstream data in the SPU buffers in alternating fashion. The SPU may shift parsing from the one SPU buffer to the other SPU buffer when parsing reaches a subset boundary within an overlap region.
摘要翻译：信息处理系统包括处理可变长度码（VLC）比特流数据的多核处理器。比特流数据包括处理器组织成功能上共同的子集的多个码字。处理器包括通用处理器（GPU）和一个或多个专用处理器（SPU）。处理器的SPU可以包括两个SPU缓冲器。处理器首先将比特流数据传输到GPU缓冲存储器中，然后用比特流数据一个接一个地填充SPU缓冲器。 SPU缓冲器可以各自包括SPU用相同比特流数据填充的重叠区域。 SPU以交替的方式解析SPU缓冲器中的位流数据。当解析达到重叠区域内的子集边界时，SPU可以将解析从一个SPU缓冲区移位到另一个SPU缓冲区。

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