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1. 发明申请

US20150006770A1 Low Latency First-In-First-Out (FIFO) Buffer 审中-公开
标题翻译：低延迟先进先出（FIFO）缓冲区
公开(公告)号：US20150006770A1
公开(公告)日：2015-01-01
申请号：US14331882
申请日：2014-07-15
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Evgeny Shumsky , Jonathan Kushnir
IPC分类号： G06F5/12 , G06F5/06
CPC分类号： G06F5/12 , G06F5/065 , G06F5/14 , G06F5/16 , G06F2205/065 , G06F2205/126
摘要： Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.
摘要翻译：为先进先出缓冲区提供系统和方法。缓冲器包括被配置为存储从缓冲器输入接收的数据的第一子缓冲器和第二子缓冲器。第二子缓冲器被配置为存储从缓冲器输入或第一子缓冲器接收的数据，并以与在缓冲器输入处接收的数据相同的顺序将数据输出到缓冲器输出。缓冲器控制逻辑被配置为选择性地将数据从缓冲器输入或第一子缓冲器路由到第二子缓冲器，使得在缓冲器输入处接收到的数据可用于以第一子缓冲器的方式从第二子缓冲器输出，先到先得。

2. 发明授权

US09996468B1 Scalable dynamic memory management in a network device 有权
公开(公告)号：US09996468B1
公开(公告)日：2018-06-12
申请号：US13666608
申请日：2012-11-01
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Evgeny Shumsky , Shira Turgeman , Gil Levy
IPC分类号： G06F12/00 , G06F12/084
CPC分类号： G06F12/084 , G06F12/00
摘要： In a method for managing memory space in a network device two or more respective allocation requests from two or more processing cores among a plurality of processing cores sharing a memory space are received at a memory management device during a first single clock cycle of the memory management device, the two or more allocation requests requesting to allocate, to the two or more processing cores, respective buffers in the shared memory space. In response to receiving the two or more allocation requests, the memory management device allocates to the two or more processing cores, respective two or more buffers in the shared memory space. Additionally, the management device, during a second single clock cycle of the memory management device, transmits respective allocation responses to each of the two or more processing cores, wherein each allocation response includes an indication of a respective allocated buffer.

3. 发明授权

US09104531B1 Multi-core device with multi-bank memory 有权
标题翻译：具有多行存储器的多核设备
公开(公告)号：US09104531B1
公开(公告)日：2015-08-11
申请号：US13674810
申请日：2012-11-12
申请人： Marvell Israel (M.I.S.L.) Ltd.
发明人： Evgeny Shumsky
IPC分类号： G06F12/00 , G06F13/16 , G06F13/372 , G06F13/362 , G06F12/08 , G06F12/02 , G06F13/14
CPC分类号： G06F13/1626 , G06F12/0284 , G06F12/0844 , G06F13/14 , G06F13/161 , G06F13/1621 , G06F13/1642 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/1673 , G06F13/3625 , G06F13/372
摘要： Some of the embodiments of the present disclosure provide a multi-core switch device comprising a plurality of P processing cores for processing packets received from a computer network; a memory comprising a plurality of M memory banks, the plurality of processing cores and the plurality of memory banks being arranged such that the plurality of processing cores have access to multiple memory banks among the plurality of memory banks to perform corresponding memory operations; and a memory access controller coupling the plurality of processing cores to the plurality of memory banks, the memory access controller configured to selectively provide, to each of the plurality of processing cores, access to multiple memory banks among the plurality of memory banks over a number of N physical couplings such that N (i) is an integer and (ii) is less than P times M.
摘要翻译：本公开的一些实施例提供了一种多核交换设备，其包括用于处理从计算机网络接收的分组的多个P处理核心; 存储器，包括多个M个存储器组，所述多个处理核心和所述多个存储器组被布置成使得所述多个处理器核可以访问所述多个存储器组中的多个存储器组以执行相应的存储器操作; 以及存储器访问控制器，其将所述多个处理核心耦合到所述多个存储器组，所述存储器访问控制器被配置为选择性地向所述多个处理核心中的每一个提供对多个存储体之间的多个存储器组的访问，的N个物理耦合，使得N（i）是整数，（ii）小于P乘以M.

4. 发明授权

US09658951B1 Scalable high bandwidth memory in a network device 有权
公开(公告)号：US09658951B1
公开(公告)日：2017-05-23
申请号：US13666622
申请日：2012-11-01
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Evgeny Shumsky , Carmi Arad , Gil Levy , Ehud Sivan
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0223 , G06F12/0207 , G06F12/0607 , G06F2212/1016 , G06F2212/1048
摘要： In a method for storing packets in a network device, a processor and a plurality of memory banks for storing packet data during processing of packets by the processor are provided on an integrated circuit device. Each memory bank has a separate channel for transferring data. A plurality of buffers are defined such that each buffer in the plurality of buffers includes a respective memory space in more than one memory bank and less than all memory banks. A buffer of the plurality of buffers is allocated for storing a single packet or a portion of a single packet. The single packet or the portion of the single packet in the allocated buffer.

5. 发明授权

US09553820B2 Maintaining packet order in a parallel processing network device 有权
标题翻译：在并行处理网络设备中维护分组顺序
公开(公告)号：US09553820B2
公开(公告)日：2017-01-24
申请号：US14209513
申请日：2014-03-13
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Evgeny Shumsky , Gil Levy , Adar Peery , Amir Roitshtein
IPC分类号： H04L12/28 , H04L12/863 , H04L12/861 , H04L12/939 , H04L12/883
CPC分类号： H04L47/6295 , H04L47/6215 , H04L49/552 , H04L49/9015 , H04L49/9057
摘要： A plurality of packets that belong to a data flow are received and are distributed to two or more packet processing elements, wherein a packet is sent to a first packet processing element. A first instance of the packet is queued at a first packet processing element according to an order of the packet within the data flow. The first instance of the packet is caused to be transmitted when processing of the first instance is completed and the first instance of the packet is at a head of a queue at the first ordering unit. A second instance of the packet is queued at a second ordering unit. The second instance of the packet is caused to be transmitted when processing of the second instance is completed and the second instance of the packet is at a head of a queue at the second ordering unit.
摘要翻译：接收属于数据流的多个分组，并将其分配给两个或多个分组处理单元，其中分组被发送到第一分组处理单元。分组的第一实例根据数据流内的分组的顺序排队在第一分组处理单元处。当第一实例的处理完成并且分组的第一实例位于第一订购单元处的队列的头部时，使分组的第一实例被发送。分组的第二实例在第二排序单元处排队。当第二实例的处理完成并且分组的第二实例处于第二排序单元处的队列的头部时，使分组的第二实例被发送。

6. 发明授权

US09807027B2 Maintaining packet order in a multi processor network device 有权
公开(公告)号：US09807027B2
公开(公告)日：2017-10-31
申请号：US15056646
申请日：2016-02-29
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Evgeny Shumsky , Gil Levy , Adar Peery , Amir Roitshtein , Aron Wohlgemuth
IPC分类号： H04L12/863 , H04L12/939
CPC分类号： H04L47/624 , H04L47/50 , H04L47/625 , H04L49/552
摘要： A plurality of packets are received by a packet processing device, and the packets are distributed among two or more packet processing node elements for processing of the packets. The packets are assigned to respective packet classes, each class corresponding to a group of packets for which an order in which the packets were received is to be preserved. The packets are queued in respective queues corresponding to the assigned packet classes and according to an order in which the packets were received by the packet processing device. The packet processing node elements issue respective instructions indicative of processing actions to be performed with respect to the packets, and indications of at least some of the processing actions are stored. A processing action with respect to a packet is performed when the packet has reached a head of a queue corresponding to the class associated with the packet.

7. 发明授权

US09459829B2 Low latency first-in-first-out (FIFO) buffer 有权
标题翻译：低延迟先进先出（FIFO）缓冲区
公开(公告)号：US09459829B2
公开(公告)日：2016-10-04
申请号：US14331882
申请日：2014-07-15
申请人： Marvell Israel (M.I.S.L.) Ltd.
发明人： Evgeny Shumsky , Jonathan Kushnir
IPC分类号： G06F5/00 , G06F5/12 , G06F5/14 , G06F5/16 , G06F5/06
CPC分类号： G06F5/12 , G06F5/065 , G06F5/14 , G06F5/16 , G06F2205/065 , G06F2205/126
摘要： Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.
摘要翻译：为先进先出缓冲区提供系统和方法。缓冲器包括被配置为存储从缓冲器输入接收的数据的第一子缓冲器和第二子缓冲器。第二子缓冲器被配置为存储从缓冲器输入或第一子缓冲器接收的数据，并以与在缓冲器输入处接收的数据相同的顺序将数据输出到缓冲器输出。缓冲器控制逻辑被配置为选择性地将数据从缓冲器输入或第一子缓冲器路由到第二子缓冲器，使得在缓冲器输入处接收到的数据可用于以第一子缓冲器的方式从第二子缓冲器输出，先到先得。

8. 发明授权

US09455907B1 Multithreaded parallel packet processing in network devices 有权
标题翻译：网络设备中的多线程并行数据包处理
公开(公告)号：US09455907B1
公开(公告)日：2016-09-27
申请号：US14092521
申请日：2013-11-27
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Evgeny Shumsky , Gil Levy
IPC分类号： H04L12/28 , H04L12/741
CPC分类号： H04L45/74
摘要： One or more processing operations are performed on a packet at a first packet processing element of a plurality of packet processing elements of a network device. A processing state corresponding to processing of the packet is indicated in a packet processing context associated with the packet. An external processing engine is triggered for performing an additional processing operation on the packet, and processing of the packet is suspended by the first packet processing element. Subsequent to completion of the additional processing operation by the external processing engine, processing of the packet is resumed, based on the packet processing context, by a second packet processing element when the second packet processing element is available for processing of the packet and the first packet processing element is not available for processing of the packet.
摘要翻译：在网络设备的多个分组处理元件的第一分组处理元件的分组上执行一个或多个处理操作。在与分组相关联的分组处理上下文中指示与分组的处理相对应的处理状态。触发外部处理引擎，对分组执行附加处理操作，并且分组的处理由第一分组处理元件暂停。在由外部处理引擎完成附加处理操作之后，当第二分组处理单元可用于处理分组时，第二分组处理单元基于分组处理上下文恢复该分组的处理，并且第一分组处理单元不可用于处理分组。

9. 发明授权

US09276868B2 Maintaining packet order in a parallel processing network device 有权
标题翻译：在并行处理网络设备中维护分组顺序
公开(公告)号：US09276868B2
公开(公告)日：2016-03-01
申请号：US14109479
申请日：2013-12-17
申请人： Marvell Israel (M.I.S.L.) Ltd.
发明人： Evgeny Shumsky , Gil Levy , Adar Peery , Amir Roitshtein , Aron Wohlgemuth
IPC分类号： H04L12/863 , H04L12/939
CPC分类号： H04L47/624 , H04L47/50 , H04L47/625 , H04L49/552
摘要： A plurality of packets are received by a packet processing device, and the packets are distributed among two or more packet processing node elements for processing of the packets. The packets are assigned to respective packet classes, each class corresponding to a group of packets for which an order in which the packets were received is to be preserved. The packets are queued in respective queues corresponding to the assigned packet classes and according to an order in which the packets were received by the packet processing device. The packet processing node elements issue respective instructions indicative of processing actions to be performed with respect to the packets, and indications of at least some of the processing actions are stored. A processing action with respect to a packet is performed when the packet has reached a head of a queue corresponding to the class associated with the packet.
摘要翻译：多个分组由分组处理设备接收，分组分布在两个或更多个分组处理节点元素中，用于处理分组。分组被分配给相应的分组类别，每个类对应于一组分组，其中分组被接收的顺序被保留。分组在对应于所分配的分组类别的各个队列中排队，并且根据分组处理设备接收到分组的顺序。分组处理节点单元发出指示要针对分组执行的处理动作的相应指令，并且存储至少一些处理动作的指示。当分组已经到达与与分组相关联的类别对应的队列的头部时，执行关于分组的处理动作。

10. 发明申请

US20140192815A1 MAINTAINING PACKET ORDER IN A PARALLEL PROCESSING NETWORK DEVICE 有权
标题翻译：维护平行处理网络设备中的分组订单
公开(公告)号：US20140192815A1
公开(公告)日：2014-07-10
申请号：US14209513
申请日：2014-03-13
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Evgeny Shumsky , Gil Levy , Adar Peery , Amir Roitshtein
IPC分类号： H04L12/863 , H04L12/861
CPC分类号： H04L47/6295 , H04L47/6215 , H04L49/552 , H04L49/9015 , H04L49/9057
摘要： A plurality of packets that belong to a data flow are received and are distributed to two or more packet processing elements, wherein a packet is sent to a first packet processing element. A first instance of the packet is queued at a first packet processing element according to an order of the packet within the data flow. The first instance of the packet is caused to be transmitted when processing of the first instance is completed and the first instance of the packet is at a head of a queue at the first ordering unit. A second instance of the packet is queued at a second ordering unit. The second instance of the packet is caused to be transmitted when processing of the second instance is completed and the second instance of the packet is at a head of a queue at the second ordering unit.
摘要翻译：接收属于数据流的多个分组，并将其分配给两个或多个分组处理单元，其中分组被发送到第一分组处理单元。分组的第一实例根据数据流内的分组的顺序排队在第一分组处理单元处。当第一实例的处理完成并且分组的第一实例位于第一订购单元处的队列的头部时，使分组的第一实例被发送。分组的第二实例在第二排序单元处排队。当第二实例的处理完成并且分组的第二实例处于第二排序单元处的队列的头部时，使分组的第二实例被发送。

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