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1. 发明授权

US09813063B2 Method of using a field-effect transistor as a current sensing device 有权
公开(公告)号：US09813063B2
公开(公告)日：2017-11-07
申请号：US14705600
申请日：2015-05-06
申请人： Apple Inc.
发明人： Gary L. Stirk , Karthik Kadirvel
IPC分类号： H03K19/0175 , G01R31/36 , H02J7/00 , H03L7/00 , G06F13/42
CPC分类号： H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
摘要： An apparatus may include one or more registers configured to store a plurality of values, and an analog-to-digital converter (ADC). Each value of the plurality of values may correspond to a characteristic of a transistor at a respective temperature value. The ADC may be configured to generate a digital value corresponding to a difference in voltage levels between a first terminal and a second terminal of the transistor. The apparatus may further include a sensor configured to measure a temperature, and control logic configured to generate a first voltage level at a control terminal of the transistor and receive the digital value from the ADC. The control logic may be further configured to determine, during a first operational mode, a current passing through the transistor dependent upon the digital value, at least one value of the plurality of values, and the temperature.

2. 发明授权

US09680491B2 Signal processing circuit 有权
公开(公告)号：US09680491B2
公开(公告)日：2017-06-13
申请号：US15251619
申请日：2016-08-30
申请人： YOKOGAWA ELECTRIC CORPORATION
发明人： Junichi Iwashita
IPC分类号： H03M1/12 , G06F13/42
CPC分类号： H03M1/12 , G06F13/4247 , G06F13/4256
摘要： A signal processing circuit includes: a plurality of daisy chain-connected AD converters each including a data ready output terminal, a synchronizing signal input terminal, and a serial clock input terminal; a calculator connected to the data ready output terminal of any of the AD converters and for outputting a serial clock to the serial clock input terminal of each of the AD converters when a data ready signal is input; and a reset processor included in the calculator and for outputting a synchronizing signal to the synchronizing signal input terminal of each of the AD converters when an output time lag among data ready signals from each of the AD converters is detected for a predetermined number of times.

3. 发明申请

US20170075837A1 CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS 有权
标题翻译：用于接口电路的连续自适应数据采集优化
公开(公告)号：US20170075837A1
公开(公告)日：2017-03-16
申请号：US15237473
申请日：2016-08-15
申请人： Uniquify, Inc.
发明人： Jung Lee , Venkat Iyer , Brett Murdock
IPC分类号： G06F13/362 , H03K5/13 , G06F13/42
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03K2005/00019 , H03L7/08 , H03L7/0812 , H03L7/10
摘要： A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation. Several fringe timing points are sampled, whereby several of the plurality of fringe timing points are associated with each of the transition edges of the second stream of data bits input to the data interface circuit. The drift amount is compared with a drift correction threshold value and the first optimal sampling point is shifted in time by the drift amount to revise the first optimal sampling point.
摘要翻译：描述了数据接口电路，其中进行用于数据位捕获的校准调整而不干扰正常的系统操作。定义了用于采样经过训练的最佳采样点以及前导和后采样点的多个DLL捕获和延迟电路。第一数据比特流被输入到数据接口电路，并且使用第一校准方法，建立用于采样数据位输入的第一最佳采样点。在正常的系统操作期间，第二数据位流被输入到数据接口电路。执行与执行第一，第二校准方法不同的第二校准方法，由此：建立至少一个参考数据路径，用于在正常系统操作期间对输入到数据接口的第二数据位流进行采样过渡沿。多个边缘定时点被采样，其中多个边缘定时点中的几个与输入到数据接口电路的第二数据位流的每个过渡边缘相关联。将漂移量与漂移校正阈值进行比较，并且第一最佳采样点在时间上偏移漂移量以修改第一最佳采样点。

4. 发明申请

US20160295732A1 EXPANSION MODULE SYSTEM 审中-公开
标题翻译：扩展模块系统
公开(公告)号：US20160295732A1
公开(公告)日：2016-10-06
申请号：US14673742
申请日：2015-03-30
申请人： Honeywell International Inc.
发明人： Jim Triplett
IPC分类号： H05K7/02 , H01R43/16 , H01R24/60
CPC分类号： H05K7/026 , G05B19/0423 , G05B2219/21039 , G06F13/4045 , G06F13/4256 , H01R24/60 , H01R43/16 , H04L12/6418 , H05K7/1477
摘要： A system and approach that may connect communication modules together in a daisy chain fashion as an expansion bus. A communication module may be connected with a data bus and a voltage bus to a baseboard having a controller. The communication module may have a multi-port universal serial bus hub connected to the data bus from the expansion connector, an electronic device connected to the hub and the voltage regulator. Another communication module having a similar structure as the first communication module may be connected to the first communication module via a data bus between the multiport hub of the first expansion module and a universal serial bus hub of the other communication module, and may have a voltage bus connected to the voltage bus of the first communication module. More communication modules may be connected in a daisy chain or serial fashion to a preceding module, and so on in a similar manner.
摘要翻译：可以以菊花链方式将通信模块连接在一起作为扩展总线的系统和方法。通信模块可以与数据总线和电压总线连接到具有控制器的基板。通信模块可以具有从扩展连接器连接到数据总线的多端口通用串行总线集线器，连接到集线器的电子设备和电压调节器。具有与第一通信模块相似结构的另一通信模块可以经由第一扩展模块的多端口集线器和另一通信模块的通用串行总线集线器之间的数据总线连接到第一通信模块，并且可以具有电压总线连接到第一通信模块的电压总线。更多的通信模块可以以菊花链或串行方式连接到前一个模块，以此类推。

5. 发明授权

US09460035B2 Method for operating a slave node of a digital bus system 有权
标题翻译：用于操作数字总线系统的从节点的方法
公开(公告)号：US09460035B2
公开(公告)日：2016-10-04
申请号：US14264086
申请日：2014-04-29
申请人： GE Energy Power Conversion GmbH
发明人： Thorsten Opitz , Frank Wothe
IPC分类号： H04J3/24 , G06F13/362 , H04L1/00 , G06F13/42 , H04L12/40 , H04L12/403
CPC分类号： G06F13/362 , G06F13/4256 , H04L1/0083 , H04L12/40032 , H04L12/403 , H04L2012/40221 , H04L2212/00
摘要： A method for operating a slave node of a digital bus system is described. The slave node comprises two sending and receiving devices. In the bus system, an input data frame is sent to a master node in input direction. The slave node receives the input data frame by the first sending and receiving device. The slave node stores service data packets contained in the input data frame in a FIFO memory. The slave node attaches at least one process data packet of its own to a last process data packet in the input data frame. The slave node attaches the service data packets to the process data packet, which is now last, in the input data frame. The slave node sends the input data frame, which was changed in this manner, to the next node in input direction by the second sending and receiving device.
摘要翻译：描述了一种用于操作数字总线系统的从节点的方法。从节点包括两个发送和接收设备。在总线系统中，输入数据帧沿输入方向发送到主节点。从节点由第一发送和接收设备接收输入数据帧。从节点将包含在输入数据帧中的服务数据分组存储在FIFO存储器中。从节点将至少一个自身的过程数据包连接到输入数据帧中的最后一个过程数据包。从节点将服务数据分组附加到输入数据帧中的最后的过程数据分组。从节点通过第二发送和接收设备将输入数据帧以这种方式发送到输入方向的下一个节点。

6. 发明授权

US09448959B2 Two-wire communication protocol engine 有权
标题翻译：双线通信协议引擎
公开(公告)号：US09448959B2
公开(公告)日：2016-09-20
申请号：US14063886
申请日：2013-10-25
申请人： ANALOG DEVICES, INC.
发明人： William Hooper , Martin Kessler , Lewis F. Lahr , Michael Giancioppo
IPC分类号： G06F13/00 , G06F13/42 , G06F13/364 , H04B3/50 , H04L1/16 , H04L1/00
CPC分类号： G06F13/42 , G06F13/364 , G06F13/4256 , G06F13/4273 , H04B3/50 , H04L1/16 , H04L2001/0093
摘要： In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus.
摘要翻译：在示例实施例中，双线通信协议引擎管理双向多节点总线系统中的控制和数据传输，其中每个节点通过双绞线总线连接到另一节点。一些实施例包括允许跨系统同步更新配置数据的状态机，分布式中断系统，基于系统中使用的数据编码的同步模式，以及应用于通过绞线传输的数据的一部分的数据加扰对公车。多节点总线系统包括主节点和多个从节点。从节点可以通过双绞线对总线供电。

7. 发明授权

US09425778B2 Continuous adaptive data capture optimization for interface circuits 有权
标题翻译：接口电路的连续自适应数据采集优化
公开(公告)号：US09425778B2
公开(公告)日：2016-08-23
申请号：US14850792
申请日：2015-09-10
申请人： Uniquify, Inc.
发明人： Jung Lee , Venkat Iyer , Brett Murdock
IPC分类号： H03K5/13 , H03K5/14 , H03L7/10 , G06F13/16 , H03L7/08 , G11C8/18 , G11C29/02 , H03L7/081 , H03K5/00
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03K2005/00019 , H03L7/08 , H03L7/0812 , H03L7/10
摘要： A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0.
摘要翻译：公开了一种用于数据接口的连续自适应定时校准功能。对于任务数据路径，通常在上电时执行第一校准方法以建立最佳采样点。建立不影响正常系统操作的第二校准方法的参考数据路径。在最佳采样点两侧的边缘定时点检查数据位边沿转换。假设边缘跃迁的定时变化指示最佳采样点的漂移，当确定漂移量大于校正阈值时，相应地调整任务路径的最佳采样点。由于始终保持最佳采样点，所以连续校准功能无论确定任何数据位无效。此外，连续校准无需连续的交替数据位值，例如1-0-1或0-1-0。

8. 发明授权

US09413359B2 Method for clock calibration 有权
标题翻译：时钟校准方法
公开(公告)号：US09413359B2
公开(公告)日：2016-08-09
申请号：US14743174
申请日：2015-06-18
申请人： Apple Inc.
发明人： Gary L. Stirk
IPC分类号： H03K5/135 , H03L7/00
CPC分类号： H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
摘要： A system may include a plurality of devices, wherein each device of the plurality of devices has a respective clock source. A first device of the plurality of devices may be configured to generate a first clock signal. A second device of the plurality of devices may be configured to generate a second clock signal, receive the first clock signal from the first device, and modify a first frequency of the first clock signal. The second device may be further configured to adjust a second frequency of the second clock signal dependent upon the modified first frequency of the first clock signal.
摘要翻译：系统可以包括多个设备，其中多个设备中的每个设备具有相应的时钟源。多个设备中的第一设备可以被配置为产生第一时钟信号。多个设备中的第二设备可以被配置为产生第二时钟信号，从第一设备接收第一时钟信号，并修改第一时钟信号的第一频率。第二装置还可以被配置为根据第一时钟信号的修改的第一频率来调整第二时钟信号的第二频率。

9. 发明授权

US09274997B2 Point-to-point serial peripheral interface for data communication between devices configured in a daisy-chain 有权
标题翻译：点对点串行外设接口，用于以菊花链方式配置的设备之间的数据通信
公开(公告)号：US09274997B2
公开(公告)日：2016-03-01
申请号：US13461787
申请日：2012-05-02
申请人： Alan Berenbaum , Eileen Marando , Richard Wahler
发明人： Alan Berenbaum , Eileen Marando , Richard Wahler
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4256
摘要： The present disclosure provides an improved point-to-point serial peripheral interface, a system comprising an improved point-to-point serial peripheral interface, and a method for use in a system comprising an improved point-to-point serial peripheral interface. A master comprises a SPI initiating port. Each slave comprises at least one SPI receiving port and at least one SPI forwarding port. The master provides a set of SPI signals to the SPI receiving port of the first slave in the chain, and the entire SPI signals are forwarded via the SPI forwarding port of each of the slaves until the SPI transaction reaches a target slave, which is identified by an in-band device addressing mechanism.
摘要翻译：本公开提供了一种改进的点对点串行外设接口，包括改进的点对点串行外设接口的系统，以及包括改进的点对点串行外设接口的系统中使用的方法。主机包括SPI启动端口。每个从站包括至少一个SPI接收端口和至少一个SPI转发端口。主器件为链中第一个从器件的SPI接收端口提供一组SPI信号，整个SPI信号通过每个从器件的SPI转发端口转发，直到SPI事务到达目标从器件，这被识别通过带内设备寻址机制。

10. 发明授权

US08966124B1 Systems, methods, and articles of manufacture to stream data 有权
标题翻译：系统，方法和制造流程数据流
公开(公告)号：US08966124B1
公开(公告)日：2015-02-24
申请号：US13627062
申请日：2012-09-26
申请人： Ronald Norman Prusia
发明人： Ronald Norman Prusia
IPC分类号： G06F3/00 , G06F13/42 , G06F13/00 , G06F13/14 , G06F9/26
CPC分类号： G06F13/4256
摘要： Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus. The bus isolates modules like object oriented programming.
摘要翻译：流数据的系统和方法。系统允许跨多个或N个设备模块进行读/写。总线环上的器件模块在上电时（初始化过程中）配置; 该过程通知每个设备模块其相关联的地址值。每个环形设备模块分析一个地址指示字，该地址指示符字识别一个读/写操作所在的地址，并将地址指示字指定的地址与其分配的地址进行比较; 当由地址指示符字指定的地址是与设备模块相关联的地址时，设备模块从地址指示字指定的地址读取/写入地址。内存控制器（环形控制器或主总线）不需要“知道”地址命令字用于菊花链中的哪个存储器芯片/器件模块。因此，系统实施例允许在不考虑总线上的多个存储器芯片/设备模块的情况下进行流传输。总线隔离了面向对象编程的模块。

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