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1. 发明授权

US10971243B2 Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register 有权
公开(公告)号：US10971243B2
公开(公告)日：2021-04-06
申请号：US16548246
申请日：2019-08-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. Busi , John R. Goss , Paul J. Grzymkowski , Krishnendu Mondal , Kiran K. Narayan , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/38 , G11C29/44 , G11C29/40 , G11C29/56 , G11C29/00 , G11C29/36
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

2. 发明授权

US10628375B2 Method and system for enumerating digital circuits in a system-on-a-chip (SOC) 有权
公开(公告)号：US10628375B2
公开(公告)日：2020-04-21
申请号：US16506427
申请日：2019-07-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas B. Chadwick, Jr. , Michael R. Ouellette , Nancy H. Pratt
IPC分类号： G06F15/78 , G06F13/42 , G11C19/00 , G06F13/40
CPC分类号： G06F15/7817 , G06F13/4068 , G06F13/4247 , G06F13/4256 , G11C19/00
摘要： Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

3. 发明授权

US10622090B2 Arbitration for memory diagnostics 有权
公开(公告)号：US10622090B2
公开(公告)日：2020-04-14
申请号：US16145678
申请日：2018-09-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. Busi , Kevin W. Gorman , Deepak I. Hanagandi , Kiran K. Narayan , Michael R. Ouellette
IPC分类号： G11C29/56 , G11C29/12 , G01R31/3187 , G11C29/44 , G11C29/04 , G11C29/26
CPC分类号： G11C29/56008 , G01R31/3187 , G11C29/12 , G11C29/44 , G11C29/4401 , G11C2029/0401 , G11C2029/2602 , G11C2029/5602 , G11C2029/5606
摘要： A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

4. 发明授权

US10153055B2 Arbitration for memory diagnostics 有权
公开(公告)号：US10153055B2
公开(公告)日：2018-12-11
申请号：US14669056
申请日：2015-03-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. Busi , Kevin W. Gorman , Deepak I. Hanagandi , Kiran K. Narayan , Michael R. Ouellette
IPC分类号： G11C29/56 , G11C29/44 , G11C29/26 , G11C29/12 , G11C29/04 , G01R31/3187
摘要： A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

5. 发明授权

US09859019B1 Programmable counter to control memory built in self-test 有权
公开(公告)号：US09859019B1
公开(公告)日：2018-01-02
申请号：US15413974
申请日：2017-01-24
申请人： International Business Machines Corporation
发明人： Deepak I. Hanagandi , Krishnendu Mondal , Kiran K. Narayan , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/00 , G11C29/12 , G06F11/27
CPC分类号： G11C29/12015 , G06F11/27 , G11C2029/1208
摘要： A system and method control an operation of a built-in self-test (BIST) of memory devices of an integrated circuit. The method includes generating count values using a program counter, and providing a first burst of instructions to the memory devices. The method also includes controlling a chip enable signal associated with each of the memory devices according to the count values during a wait period following the providing the first burst of instructions until a second burst of instructions is provided to the memory devices. The chip enable signal of each of the memory devices defines clock cycles at which the memory device is operated and clock cycles at which the memory device is idle.

6. 发明授权

US09715942B2 Built-in self-test (BIST) circuit and associated BIST method for embedded memories 有权
公开(公告)号：US09715942B2
公开(公告)日：2017-07-25
申请号：US14734041
申请日：2015-06-09
申请人： International Business Machines Corporation
发明人： Aravindan J. Busi , Deepak I. Hanagandi , Krishnendu Mondal , Michael R. Ouellette
IPC分类号： G01R31/28 , G11C29/18 , G11C29/36 , G11C29/38
CPC分类号： G11C29/18 , G11C29/36 , G11C29/38
摘要： Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

7. 发明授权

US09672185B2 Method and system for enumerating digital circuits in a system-on-a-chip (SOC) 有权
公开(公告)号：US09672185B2
公开(公告)日：2017-06-06
申请号：US14040165
申请日：2013-09-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas B. Chadwick, Jr. , Michael R. Ouellette , Nancy H. Pratt
IPC分类号： G06F13/42
CPC分类号： G06F15/7817 , G06F13/4068 , G06F13/4247 , G06F13/4256 , G11C19/00
摘要： Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

8. 发明申请

US20140129888A1 STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES 有权
标题翻译：突击控制器和主机启动
公开(公告)号：US20140129888A1
公开(公告)日：2014-05-08
申请号：US13671605
申请日：2012-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Valerie H. Chickanosky , Kevin W. Gorman , Suzanne Granato , Michael R. Ouellette , Nancy H. Pratt , Michael A. Ziegerhofer
IPC分类号： G01R31/3177
CPC分类号： G01R31/31724
摘要： Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.
摘要翻译：每个内置自检（BIST）控制器中的每个寄存器包含与至少一个其他BIST控制器特定启动计数不同的BIST控制器特定的起始计数值。测试控制器同时向所有BIST控制器提供启动命令。这使得每个BIST控制器使用计数器同时开始BIST控制器特定的开始计数值的倒计时。每个BIST控制器在倒计时完成时（在相应的BIST控制器中），在对应的BIST域中启动测试过程。因此，根据不同寄存器中BIST控制器特定的开始计数值的差异，测试过程在至少两个BIST域中的不同时间开始。此外，在测试过程中，每个交错控制器可以错开交错控制器所连接的相应BIST域内的每个BIST引擎的开始。

9. 发明授权

US10628376B2 Method and system for enumerating digital circuits in a system-on-a-chip (SOC) 有权
公开(公告)号：US10628376B2
公开(公告)日：2020-04-21
申请号：US16508964
申请日：2019-07-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas B. Chadwick, Jr. , Michael R. Ouellette , Nancy H. Pratt
IPC分类号： G06F15/78 , G06F13/42 , G11C19/00 , G06F13/40
CPC分类号： G06F15/7817 , G06F13/4068 , G06F13/4247 , G06F13/4256 , G11C19/00
摘要： Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

10. 发明授权

US10553302B2 Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register 有权
公开(公告)号：US10553302B2
公开(公告)日：2020-02-04
申请号：US15798858
申请日：2017-10-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. Busi , John R. Goss , Paul J. Grzymkowski , Krishnendu Mondal , Kiran K. Narayan , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/38 , G11C29/44 , G11C29/40 , G11C29/56 , G11C29/00 , G11C29/36
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

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