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1. 发明授权

US10971243B2 Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register 有权
公开(公告)号：US10971243B2
公开(公告)日：2021-04-06
申请号：US16548246
申请日：2019-08-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. Busi , John R. Goss , Paul J. Grzymkowski , Krishnendu Mondal , Kiran K. Narayan , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/38 , G11C29/44 , G11C29/40 , G11C29/56 , G11C29/00 , G11C29/36
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

2. 发明授权

US10153055B2 Arbitration for memory diagnostics 有权
公开(公告)号：US10153055B2
公开(公告)日：2018-12-11
申请号：US14669056
申请日：2015-03-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. Busi , Kevin W. Gorman , Deepak I. Hanagandi , Kiran K. Narayan , Michael R. Ouellette
IPC分类号： G11C29/56 , G11C29/44 , G11C29/26 , G11C29/12 , G11C29/04 , G01R31/3187
摘要： A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

3. 发明授权

US09859019B1 Programmable counter to control memory built in self-test 有权
公开(公告)号：US09859019B1
公开(公告)日：2018-01-02
申请号：US15413974
申请日：2017-01-24
申请人： International Business Machines Corporation
发明人： Deepak I. Hanagandi , Krishnendu Mondal , Kiran K. Narayan , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/00 , G11C29/12 , G06F11/27
CPC分类号： G11C29/12015 , G06F11/27 , G11C2029/1208
摘要： A system and method control an operation of a built-in self-test (BIST) of memory devices of an integrated circuit. The method includes generating count values using a program counter, and providing a first burst of instructions to the memory devices. The method also includes controlling a chip enable signal associated with each of the memory devices according to the count values during a wait period following the providing the first burst of instructions until a second burst of instructions is provided to the memory devices. The chip enable signal of each of the memory devices defines clock cycles at which the memory device is operated and clock cycles at which the memory device is idle.

4. 发明授权

US09715942B2 Built-in self-test (BIST) circuit and associated BIST method for embedded memories 有权
公开(公告)号：US09715942B2
公开(公告)日：2017-07-25
申请号：US14734041
申请日：2015-06-09
申请人： International Business Machines Corporation
发明人： Aravindan J. Busi , Deepak I. Hanagandi , Krishnendu Mondal , Michael R. Ouellette
IPC分类号： G01R31/28 , G11C29/18 , G11C29/36 , G11C29/38
CPC分类号： G11C29/18 , G11C29/36 , G11C29/38
摘要： Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

5. 发明授权

US09672185B2 Method and system for enumerating digital circuits in a system-on-a-chip (SOC) 有权
公开(公告)号：US09672185B2
公开(公告)日：2017-06-06
申请号：US14040165
申请日：2013-09-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas B. Chadwick, Jr. , Michael R. Ouellette , Nancy H. Pratt
IPC分类号： G06F13/42
CPC分类号： G06F15/7817 , G06F13/4068 , G06F13/4247 , G06F13/4256 , G11C19/00
摘要： Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

6. 发明申请

US20140129888A1 STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES 有权
标题翻译：突击控制器和主机启动
公开(公告)号：US20140129888A1
公开(公告)日：2014-05-08
申请号：US13671605
申请日：2012-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Valerie H. Chickanosky , Kevin W. Gorman , Suzanne Granato , Michael R. Ouellette , Nancy H. Pratt , Michael A. Ziegerhofer
IPC分类号： G01R31/3177
CPC分类号： G01R31/31724
摘要： Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.
摘要翻译：每个内置自检（BIST）控制器中的每个寄存器包含与至少一个其他BIST控制器特定启动计数不同的BIST控制器特定的起始计数值。测试控制器同时向所有BIST控制器提供启动命令。这使得每个BIST控制器使用计数器同时开始BIST控制器特定的开始计数值的倒计时。每个BIST控制器在倒计时完成时（在相应的BIST控制器中），在对应的BIST域中启动测试过程。因此，根据不同寄存器中BIST控制器特定的开始计数值的差异，测试过程在至少两个BIST域中的不同时间开始。此外，在测试过程中，每个交错控制器可以错开交错控制器所连接的相应BIST域内的每个BIST引擎的开始。

7. 发明授权

US10553302B2 Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register 有权
公开(公告)号：US10553302B2
公开(公告)日：2020-02-04
申请号：US15798858
申请日：2017-10-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. Busi , John R. Goss , Paul J. Grzymkowski , Krishnendu Mondal , Kiran K. Narayan , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/38 , G11C29/44 , G11C29/40 , G11C29/56 , G11C29/00 , G11C29/36
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

8. 发明授权

US09460811B2 Read only memory (ROM) with redundancy 有权
标题翻译：只读存储器（ROM）冗余
公开(公告)号：US09460811B2
公开(公告)日：2016-10-04
申请号：US14453779
申请日：2014-08-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G11C29/00 , G11C29/12 , G11C29/44 , G06F11/07 , G11C17/00
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译：提供了具有冗余性和使用方法的只读存储器（ROM）。具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。

9. 发明申请

US20150039950A1 APPARATUS FOR CAPTURING RESULTS OF MEMORY TESTING 有权
标题翻译：用于记录测试结果的装置
公开(公告)号：US20150039950A1
公开(公告)日：2015-02-05
申请号：US13955401
申请日：2013-07-31
申请人： International Business Machines Corporation
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
IPC分类号： G06F11/27
CPC分类号： G06F11/27 , G11C29/44 , G11C29/56008 , G11C2029/1208 , G11C2029/4402 , G11C2029/5606
摘要： A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.
摘要翻译：一种用于产生联合测试动作组（JTAG）捕捉移位测试数据寄存器的描述文件的方法，用于解释包含在被配置用于测试集成电路存储器的集成电路结构中的存储器的测试结果。计算机从第一数据文件中提取内置于自检实例中的内存的名称，内置于自测试端口名称的内存和第一存储器的名称。第一个数据文件控制集成电路组件的分层结构和架构布置。第一数据文件描述了组件的结构布置，电路径以及组件与集成电路设计的电路之间的连接的分级顺序。计算机将提取的名称添加到描述文件中，使得描述文件被配置为解释存储器的测试结果。

10. 发明申请

US20140189448A1 DECREASING POWER SUPPLY DEMAND DURING BIST INITIALIZATIONS 有权
标题翻译：在BIST初始化期间减少供电需求
公开(公告)号：US20140189448A1
公开(公告)日：2014-07-03
申请号：US13732711
申请日：2013-01-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Deepak I. Hanagandi , Krishnendu Mondal , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/12
CPC分类号： G11C29/12015 , G11C29/12005 , G11C29/16 , G11C29/26 , G11C2029/2602
摘要： Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.
摘要翻译：本发明的方面提供了在内置自检（BIST）初始化期间降低供电需求。在一个实施例中，用于在BIST初始化期间减少电源需求的BIST架构包括：一系列缓慢的BIST I / O接口; 一连串快速BIST I / O接口，每个快速BIST I / O接口连接到一个缓慢的BIST I / O接口; 以及BIST引擎，其包括用于控制每个慢BIST I / O接口内的复用器的突发交错锁存器，其中针对第一突发信号的脉冲串交错锁存器将第一突发信号交错到每个慢BIST I / O 接口，使得在第一时钟周期期间，仅第一慢BIST I / O接口接收第一个突发信号。

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