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1. 发明申请

US20180041375A1 COMMUNICATION DEVICE, COMMUNICATION METHOD, AND COMPUTER READABLE MEDIUM 审中-公开
公开(公告)号：US20180041375A1
公开(公告)日：2018-02-08
申请号：US15549079
申请日：2015-02-20
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Kiyofumi TAKEUCHI
IPC分类号： H04L29/08 , G06F13/40
CPC分类号： H04L29/08954 , G05B2219/2231 , G06F13/4054 , H04L12/40 , H04L12/40013 , H04L12/40019 , H04L29/06 , H04L67/322 , H04L69/28
摘要： A communication device (100) to transmit a first communication frame and also transmit a second communication frame having a lower priority than a priority of transmitting the first communication frame includes a communication arbitration unit (107) to acquire, when a transmission request for the first communication frame has occurred during transmission of the second communication frame, an allowed time of a time required before a master device starts receiving the first communication frame, a remaining time until completion of the transmission of the second communication frame, and a necessary time required before the master device starts receiving the first communication frame, and determine whether to continue the transmission of the second communication frame on the basis of the allowed time, the remaining time, and the necessary time that have been acquired.

2. 发明授权

US09507744B2 Handling two SGPIO channels using single SGPIO decoder on a backplane controller 有权
标题翻译：在背板控制器上使用单个SGPIO解码器处理两个SGPIO通道
公开(公告)号：US09507744B2
公开(公告)日：2016-11-29
申请号：US14100613
申请日：2013-12-09
申请人： AMERICAN MEGATRENDS, INC.
发明人： Kayalvizhi Dhandapani
IPC分类号： H05K7/10 , G06F13/40 , G06F13/38
CPC分类号： G06F13/4054 , G06F13/385 , G06F13/4068 , G06F13/409
摘要： An aspect of present disclosure relates to a computer-implemented method for handling two SGPIO channels by using one SGPIO decoder. The method includes: (a) establishing communication between a backplane controller and a host computer through HBA, (b) receiving control commands and control data for monitoring and controlling a first and a second group of drive slots, (c) checking a clock signal having a first time period and a second time period, (d) forwarding the control commands and control data for the first group to the first group of drive slots during first time period, and forwarding the control commands and control data for the second group to the second group of drive slots during second time period, (e) receiving responses from first and second group of drive slots, respectively, and (f) sending the responses from first and second group of drive slots to the host computer.
摘要翻译：本公开的一个方面涉及一种通过使用一个SGPIO解码器来处理两个SGPIO信道的计算机实现的方法。该方法包括：（a）通过HBA建立背板控制器和主计算机之间的通信，（b）接收控制命令和控制数据，用于监视和控制第一组和第二组驱动器时隙，（c）检查时钟信号具有第一时间段和第二时间段，（d）在第一时间段期间将用于第一组的控制命令和控制数据转发到第一组驱动器时隙，并且将第二组的控制命令和控制数据转发到在第二时间段期间的第二组驱动器插槽，（e）分别接收来自第一组和第二组驱动器插槽的响应，以及（f）将来自第一组和第二组驱动器时隙的响应发送到主机。

3. 发明授权

US08904078B2 High speed serial peripheral interface system 有权
标题翻译：高速串行外设接口系统
公开(公告)号：US08904078B2
公开(公告)日：2014-12-02
申请号：US13657501
申请日：2012-10-22
申请人： International Business Machines Corporation
发明人： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F13/20 , G06F13/42 , G06F13/00 , G06F13/36
CPC分类号： G06F13/4291 , G06F13/4054
摘要： A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.
摘要翻译：公开了一种包括总线适配器的串行外设接口（SPI）系统。总线适配器可以包括数据转换器，其可以适于从第一主输出外围输入（MOPI）线和来自SPI主器件的芯片选择线接收相应的第一和第二数据。数据转换器还可以适于交织第一和第二数据，并且数据转换器可以适于在第二MOPI线上与第二时钟信号同步地发送交错的第一和第二数据。总线适配器还可以包括适于产生第二时钟信号以传输到SPI外围设备的时钟速率调节器。第二时钟信号可以适于使得SPI外围设备能够读取所发送的数据。

4. 发明授权

US08843687B2 Semiconductor device controlling outbound and inbound path switching sections based on a setting state and controlling method thereof 有权
标题翻译：基于设置状态及其控制方法控制出站和入站路径切换部分的半导体设备
公开(公告)号：US08843687B2
公开(公告)日：2014-09-23
申请号：US13472655
申请日：2012-05-16
申请人： Hisae Kita , Tatsuhiro Suzumura
发明人： Hisae Kita , Tatsuhiro Suzumura
IPC分类号： G06F13/00
CPC分类号： G06F13/4054
摘要： According to one embodiment, a semiconductor device includes a storing section that stores a setting state that is one of a first connecting state in which another end of a first outbound system bus is connected to an outbound output terminal and another end of a first inbound system bus is connected to an inbound output terminal, and a second connecting state in which another end of a second outbound system bus is connected to the outbound output terminal and another end of a second inbound system bus is connected to the inbound output terminal; and a control section that controls an outbound path switching section and an inbound path switching section based on the setting state so as to assume one of the first connecting state and the second connecting state.
摘要翻译：根据一个实施例，半导体器件包括存储部分，其存储作为第一连接状态之一的设置状态，其中第一出站系统总线的另一端连接到出站输出终端，第一入站系统的另一端总线连接到入站输出端子，第二连接状态，其中第二出站系统总线的另一端连接到出站输出端，第二入站系统总线的另一端连接到入站输出端; 以及控制部，其基于设定状态来控制出站路径切换部和入站路径切换部，以便呈现第一连接状态和第二连接状态中的一个。

5. 发明授权

US08826057B1 Multiple time domain synchronizer circuits 有权
标题翻译：多个时域同步器电路
公开(公告)号：US08826057B1
公开(公告)日：2014-09-02
申请号：US13538643
申请日：2012-06-29
申请人： Bruce Lorenz Chin , David Stuart Gibson
发明人： Bruce Lorenz Chin , David Stuart Gibson
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00
CPC分类号： G11C7/1084 , G06F13/4054 , G11C7/109 , G11C7/1093 , H04L7/0045
摘要： A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.
摘要翻译：多时域同步器包括其中包含多个串联连接的延迟元件的数据流水线。提供了一种等待时间选择电路，其具有电耦合到数据流水线中对应的多个延迟元件的输出的多个输入。等待时间选择电路被配置为响应于等待时间控制信号而从多个延迟元件中选择的一个的输出传递数据流水线信号。提供同步电路，其电连接到等待时间选择电路的输出端。该同步电路包括其中的第一和第二不相等的定时路径，其响应于等待时间选择电路选择的数据流水线信号的捕获与选择第一和第二不等时序路径之一的目的地代码的时钟被捕获的数据流水线信号遍历为活动状态。

6. 发明申请

US20130151742A1 SEMICONDUCTOR DEVICE AND CONTROLLING METHOD THEREOF 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20130151742A1
公开(公告)日：2013-06-13
申请号：US13472655
申请日：2012-05-16
申请人： Hisae Kita , Tatsuhiro Suzumura
发明人： Hisae Kita , Tatsuhiro Suzumura
IPC分类号： G06F13/00
CPC分类号： G06F13/4054
摘要： According to one embodiment, a semiconductor device includes a storing section that stores a setting state that is one of a first connecting state in which another end of a first outbound system bus is connected to an outbound output terminal and another end of a first inbound system bus is connected to an inbound output terminal, and a second connecting state in which another end of a second outbound system bus is connected to the outbound output terminal and another end of a second inbound system bus is connected to the inbound output terminal; and a control section that controls an outbound path switching section and an inbound path switching section based on the setting state so as to assume one of the first connecting state and the second connecting state.
摘要翻译：根据一个实施例，半导体器件包括存储部分，其存储作为第一连接状态之一的设置状态，其中第一出站系统总线的另一端连接到出站输出终端，第一入站系统的另一端总线连接到入站输出端子，第二连接状态，其中第二出站系统总线的另一端连接到出站输出端，第二入站系统总线的另一端连接到入站输出端; 以及控制部，其基于设定状态来控制出站路径切换部和入站路径切换部，以便呈现第一连接状态和第二连接状态中的一个。

7. 发明授权

US08296482B2 Translating requests between full speed bus and slower speed device wherein the translation logic is based on snoop result and modified cache state 有权
标题翻译：在全速总线和速度较慢的设备之间转换请求，其中翻译逻辑基于侦听结果和修改的高速缓存状态
公开(公告)号：US08296482B2
公开(公告)日：2012-10-23
申请号：US12824188
申请日：2010-06-27
申请人： Thomas S. Cummins , Kris W. Utermark
发明人： Thomas S. Cummins , Kris W. Utermark
IPC分类号： G06F12/10 , G06F13/00
CPC分类号： G06F13/4054 , G06F13/28 , G06F2213/0038
摘要： Methods and apparatus related to techniques for translating requests between a full speed bus and a slower speed device are described. In one embodiment, a translation logic translates requests between a full speed bus (such as a front side bus, e.g., running relatively higher frequencies, for example at MHz levels) and a much slower speed device (such as a System On Chip (SOC) device (or SOC Device Under Test (DUT)), e.g., logic provided through emulation, which may be running at much lower frequency, for example kHz levels). Other embodiments are also disclosed.
摘要翻译：描述与全速总线和较慢速度设备之间的请求转换技术相关的方法和设备。在一个实施例中，翻译逻辑将全速总线（例如，前端总线，例如，以较高的频率运行，例如在MHz级别）和较慢速的设备（例如片上系统（SOC））器件（或SOC被测试器件（DUT）），例如，通过仿真提供的逻辑，其可以以低得多的频率运行，例如kHz电平）。还公开了其他实施例。

8. 发明授权

US07616560B2 Bus system consisting of at least two data buses 有权
标题翻译：总线系统由至少两条数据总线组成
公开(公告)号：US07616560B2
公开(公告)日：2009-11-10
申请号：US10471515
申请日：2002-03-14
申请人： Thomas Fuehrer , Bernd Mueller , Florian Hartwich , Robert Hugel
发明人： Thomas Fuehrer , Bernd Mueller , Florian Hartwich , Robert Hugel
IPC分类号： H04J1/16 , H04J3/06 , H04L12/56 , G06F11/00
CPC分类号： G06F11/008 , G05B2219/25031 , G06F13/4054 , G06F13/4286 , H04J3/0652 , H04L12/4625 , H04L12/66 , H04L2012/40241
摘要： A bus system includes at least two data buses, the first data bus having a first number of users and the second data bus having a second number of users. At least two TTCAN buses, which are interlinked by users connected simultaneously to both TTCAN buses, are used as the data buses. Fewer users than the sum of the number of users of the first TTCAN bus and the number of users of the second TTCAN bus are connected to the two TTCAN buses at the same time. A generating arrangement is included to generate a scalable fault tolerance in the bus system as a function of the number of users connected to the at least two TTCAN buses at the same time.
摘要翻译：总线系统包括至少两个数据总线，第一数据总线具有第一数量的用户，第二数据总线具有第二数量的用户。至少两台由同时连接到两台TTCAN总线的用户互连的TTCAN总线用作数据总线。与第一台TTCAN总线的用户总数和第二台TTCAN总线的用户总数相同的用户数量同时连接到两台TTCAN总线。包括生成装置，以便在总线系统中产生可伸缩的容错，作为同时连接到至少两个TTCAN总线的用户数量的函数。

9. 发明申请

US20080195882A1 Method and device for synchronizing cycle time of a plurality of TTCAN buses based on determined global time deviations and a corresponding bus system 有权
标题翻译：用于基于确定的全局时间偏差和相应的总线系统来同步多个TTCAN总线的周期时间的方法和装置
公开(公告)号：US20080195882A1
公开(公告)日：2008-08-14
申请号：US12148051
申请日：2008-04-15
申请人： Thomas FUEHRER , Bernd MUELLER , Florian HARTWICH , Robert HUGEL
发明人： Thomas FUEHRER , Bernd MUELLER , Florian HARTWICH , Robert HUGEL
IPC分类号： G06F13/14 , G06F1/12
CPC分类号： G06F11/008 , G05B2219/25031 , G06F13/4054 , G06F13/4286 , H04J3/0652 , H04L12/4625 , H04L12/66 , H04L2012/40241
摘要： A method, a device, and a bus system for synchronizing at least two TTCAN buses having at least one bus user, there being cycle times of the basic cycles in the TTCAN buses, a global time being determined in each TTCAN bus and the deviations of the global times of the TTCAN buses which are linked together by at least one user being determined from the global times, and the deviations of the individual global times being transmitted to at least one bus user, the cycle times of the TTCAN buses, which are connected by at least one user, being mutually adjusted as a function of the deviations in the global times in such a way that the buses are synchronized with respect to the cycle times.
摘要翻译：一种用于使具有至少一个总线用户的至少两个TTCAN总线同步的方法，装置和总线系统，在TTCAN总线中存在基本周期的周期时间，每个TTCAN总线中确定的全局时间和由全球时间确定的至少一个用户链接在一起的TTCAN总线的全球时间，以及发送给至少一个总线用户的各个全球时间的偏差，TTCAN总线的周期时间通过至少一个用户连接，以与总体相对于循环时间同步的方式相互调整为全局时间中的偏差的函数。

10. 发明授权

US07305510B2 Multiple master buses and slave buses transmitting simultaneously 有权
标题翻译：多个主总线和从属总线同时传输
公开(公告)号：US07305510B2
公开(公告)日：2007-12-04
申请号：US10877376
申请日：2004-06-25
申请人： William V. Miller
发明人： William V. Miller
IPC分类号： G06F13/40 , G00F13/00
CPC分类号： G06F13/4054
摘要： A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses and a slave bus connected to the multi-bus interface. The multi-bus interface enables one master bus at a time to access the slave bus. Also disclosed herein are bus structures and methods for interfacing between master buses and slave buses.
摘要翻译：本文公开了一种总线系统，例如位于数字设备内部的内部总线系统。总线系统包括多个主总线，每个主总线连接到至少一个主站。总线系统还包括连接到多个主总线的多总线接口和连接到多总线接口的从总线。多总线接口使一个主总线能够一次访问从总线。这里还公开了用于在主总线和从属总线之间进行接口的总线结构和方法。

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