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    • 1. 发明授权
    • Thin film electroluminescent edge emitter structure on a silcon substrate
    • 硅衬底上的薄膜电致发光边缘发射极结构
    • US5004956A
    • 1991-04-02
    • US273296
    • 1988-11-18
    • Zoltan K. KunMichael W. CresswellRichard H. Hopkins
    • Zoltan K. KunMichael W. CresswellRichard H. Hopkins
    • B41J2/447H05B33/06H05B33/10H05B33/12H05B33/22H05B33/26
    • B41J2/45H05B33/06H05B33/10H05B33/12H05B33/22H05B33/26Y10S428/917
    • A thin film electroluminescent edge emitter assembly includes a substrate layer having a configuration to define at least one lateral edge surface and at least one integrated circuit formed therein. The integrated circuit has an input for receiving logic signals, and has an excitation voltage input and a plurality of output leads. The output leads form control electrodes each having an end portion terminating at the substrate lateral edge surface. The integrated circuit is operable to provide an excitation voltage to selected control electrodes in response to preselected logic signals provided to the integrated circuit at the logic signal input. A laminar arrangement formed from a first dielectric layer, a second dielectric layer, a phosphor layer interposed between the first and second dielectric layers and a common electrode layer is disposed on the end portions of the control electrodes. These various layers define a plurality of pixels each having a light-emitting face at the substrate lateral edge surface. Pixels associated with the selected control electrodes are responsive to the excitation voltage provided to the selected control electrodes to radiate a light signal emitted at the pixel light emitting faces.
    • 薄膜电致发光边缘发射器组件包括具有限定至少一个侧边缘表面的构造的基底层和形成在其中的至少一个集成电路。 集成电路具有用于接收逻辑信号的输入,并且具有激励电压输入和多个输出引线。 输出引线形成控制电极,每个控制电极的端部终止于基板侧边缘表面。 集成电路可操作以响应于在逻辑信号输入处提供给集成电路的预选逻辑信号,向选定的控制电极提供激励电压。 由控制电极的端部设置由第一电介质层,第二电介质层,介于第一和第二电介质层之间的荧光体层和公共电极层形成的层叠布置。 这些各种层限定了多个像素,每个像素在衬底侧边缘表面具有发光面。 与所选择的控制电极相关联的像素响应于提供给所选择的控制电极的激发电压,以辐射在像素发光面发射的光信号。
    • 2. 发明授权
    • Thin film electroluminescent edge emitter structure on a silicon
substrate
    • 硅衬底上的薄膜电致发光边缘发射极结构
    • US5043631A
    • 1991-08-27
    • US235143
    • 1988-08-23
    • Zoltan K. KunMichael W. CresswellRichard H. Hopkins
    • Zoltan K. KunMichael W. CresswellRichard H. Hopkins
    • H05B33/06H05B33/10H05B33/12H05B33/22H05B33/26
    • H05B33/26H05B33/06H05B33/10H05B33/12H05B33/22Y10S428/917
    • A thin film electroluminescent edge emitter assembly includes a substrate layer having a configuration to define at least one lateral edge surface and at least one integrated circuit formed therein. The integrated circuit has an input for receiving logic signals, and has an excitation voltage input and a plurality of output leads. The output leads form control electrodes each having an end portion terminating at the substrate lateral edge surface. The integrated circuit is operable to provide an excitation voltage to selected control electrodes in response to preselected logic signals provided to the integrated circuit at the logic signal input.A laminar arrangement formed from a first dielectric layer, a second dielectric layer, a phosphor layer interposed between the first and second dielectric layers and a common electrode layer is disposed on the end portions of the control electrodes. These various layers define a plurality of pixels each having a light-emitting face at the substrate lateral edge surface. Pixels associated with the selected control electrodes are responsive to the excitation voltage provided to the selected control electrodes to radiate a light signal emitted at the pixel light emitting faces.
    • 薄膜电致发光边缘发射器组件包括具有限定至少一个侧边缘表面的构造的基底层和形成在其中的至少一个集成电路。 集成电路具有用于接收逻辑信号的输入,并且具有激励电压输入和多个输出引线。 输出引线形成控制电极,每个控制电极的端部终止于基板侧边缘表面。 集成电路可操作以响应于在逻辑信号输入处提供给集成电路的预选逻辑信号,向选定的控制电极提供激励电压。 由控制电极的端部设置由第一电介质层,第二电介质层,介于第一和第二电介质层之间的荧光体层和公共电极层形成的层叠布置。 这些各种层限定了多个像素,每个像素在衬底侧边缘表面具有发光面。 与所选择的控制电极相关联的像素响应于提供给所选择的控制电极的激发电压,以辐射在像素发光面发射的光信号。
    • 3. 发明授权
    • Method of producing large diameter silicon carbide crystals
    • 生产大直径碳化硅晶体的方法
    • US5746827A
    • 1998-05-05
    • US579277
    • 1995-12-27
    • Donovan L. BarrettRichard N. ThomasRaymond G. Seidensticker, deceasedRichard H. Hopkins
    • Donovan L. BarrettRichard N. ThomasRaymond G. Seidensticker, deceasedRichard H. Hopkins
    • C30B23/00
    • C30B23/00C30B29/36
    • A method for producing crystals of silicon carbide in a furnace. The furnace has a crucible with a cavity in which the cavity has first and second spaced-apart regions. The crucible cavity of the furnace is capable of being heated, preferably by induction or resistance heating, with insulation placed around the crucible and crucible cavity. A source material of silicon carbide is provided at the first region of the crucible cavity, and a monocrystalline seed is placed at the second region of the crucible cavity. A first growth stage is then conducted in which the first region and the second region of the crucible cavity are heated to at least the sublimation temperature of silicon carbide under substantially isothermal conditions. Then, a second growth stage is conducted in which a temperature gradient is provided between the first and the second region of the crucible cavity, such that the seed in the second crucible region is kept at a temperature lower than a temperature of the first crucible region.
    • 一种在炉中制造碳化硅晶体的方法。 炉具有具有空腔的坩埚,其中空腔具有第一和第二间隔开的区域。 炉的坩埚腔能够被加热,优选地通过感应或电阻加热,绝缘体放置在坩埚和坩埚腔周围。 碳坩埚的源材料设置在坩埚腔的第一区域,单晶种子放置在坩埚腔的第二区域。 然后进行第一生长阶段,其中坩埚腔的第一区域和第二区域在基本上等温条件下被加热至至少碳化硅的升华温度。 然后,进行第二生长阶段,其中在坩埚腔的第一和第二区域之间设置温度梯度,使得第二坩埚区域中的种子保持在比第一坩埚区域的温度低的温度 。
    • 10. 发明申请
    • Low-Doped Semi-Insulating Sic Crystals and Method
    • 低掺杂半绝缘矽晶体和方法
    • US20080190355A1
    • 2008-08-14
    • US11629584
    • 2005-07-06
    • Jihong ChenIlya ZwiebackAvinash K. GuptaDonovan L. BarrettRichard H. HopkinsEdward SemenasThomas A. AndersonAndrew E. Souzis
    • Jihong ChenIlya ZwiebackAvinash K. GuptaDonovan L. BarrettRichard H. HopkinsEdward SemenasThomas A. AndersonAndrew E. Souzis
    • C30B33/02H01B1/02
    • H01L29/1608C30B23/00C30B29/36H01L21/02378H01L21/02529H01L21/02581H01L21/02631
    • The invention relates to substrates of semi-insulating silicon carbide used for semiconductor devices and a method for making the same. The substrates have a resistivity above 106 Ohm-cm, and preferably above 108 Ohm-cm, and most preferably above 109 Ohm-cm, and a capacitance below 5 pF/mm2 and preferably below 1 pF/mm2. The electrical properties of the substrates are controlled by a small amount of added deep level impurity, large enough in concentration to dominate the electrical behavior, but small enough to avoid structural defects. The substrates have concentrations of unintentional background impurities, including shallow donors and acceptors, purposely reduced to below 5·1016 cm−3, and preferably to below 1·1016 cm−3, and the concentration of deep level impurity is higher, and preferably at least two times higher, than the difference between the concentrations of shallow acceptors and shallow donors. The deep level impurity comprises one of selected metals from the periodic groups IB, IIB, IIIB, IVB, VB, VIB, VIIB and VIIIB. Vanadium is a preferred deep level element. In addition to controlling the resistivity and capacitance, a further advantage of the invention is an increase in electrical uniformity over the entire crystal and reduction in the density of crystal defects.
    • 本发明涉及用于半导体器件的半绝缘碳化硅的衬底及其制造方法。 基板的电阻率高于106欧姆 - 厘米,优选高于108欧姆 - 厘米,最优选高于109欧姆 - 厘米,电容低于5 pF / mm2,最好低于1 pF / mm2。 基板的电学特性由少量的加入的深度杂质控制,其浓度足够大以控制电气行为,但足够小以避免结构缺陷。 底物具有无意的背景杂质浓度,包括浅供体和受体,故意降低至5.1016cm-3以下,优选低于1.1016cm-3,深层杂质的浓度较高,优选至少高两倍 ,比浅受体和浅供体的浓度之间的差异。 深层杂质包括选自周期性基团IB,IIB,IIIB,IVB,VB,VIB,VIIB和VIIIB的金属之一。 钒是首选的深层元素。 除了控制电阻率和电容之外,本发明的另一个优点是在整个晶体上的电均匀性的增加和晶体缺陷密度的降低。