专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06022410A Alkaline-earth metal silicides on silicon 失效
标题翻译：硅上的碱土金属硅化物
公开(公告)号：US06022410A
公开(公告)日：2000-02-08
申请号：US144921
申请日：1998-09-01
申请人： Zhiyi Yu , Jun Wang , Ravindranath Droopad , Daniel S. Marshall , Jerald A. Hallmark , Jonathan K. Abrokwah
发明人： Zhiyi Yu , Jun Wang , Ravindranath Droopad , Daniel S. Marshall , Jerald A. Hallmark , Jonathan K. Abrokwah
IPC分类号： H01L21/203 , C30B23/02 , C30B29/10 , C30B23/00
CPC分类号： C30B23/02 , C30B29/10
摘要： A method of forming a thin silicide layer on a silicon substrate 12 including heating the surface of the substrate to a temperature of approximately 500.degree. C. to 750.degree. C. and directing an atomic beam of silicon 18 and an atomic beam of an alkaline-earth metal 20 at the heated surface of the substrate in a molecular beam epitaxy chamber at a pressure in a range below 10.sup.-9 Torr. The silicon to alkaline-earth metal flux ratio is kept constant (e.g. Si/Ba flux ratio is kept at approximately 2:1) so as to form a thin alkaline-earth metal silicide layer (e.g. BaSi.sub.2) on the surface of the substrate. The thickness is determined by monitoring in situ the surface of the single crystal silicide layer with RHEED and terminating the atomic beam when the silicide layer is a selected submonolayer to one monolayer thick.
摘要翻译：一种在硅衬底12上形成薄硅化物层的方法，包括将衬底的表面加热至约500℃至750℃的温度，并引导硅18的原子束和碱性电子束的原子束，在分子束外延室中的衬底的加热表面处的压力在10-9乇以下的地球金属20。将硅与碱土金属的通量比保持恒定（例如，Si / Ba通量比保持在约2:1），以在衬底的表面上形成薄的碱土金属硅化物层（例如BaSi 2）。通过用RHEED原位监测单晶硅化物层的表面并且当硅化物层是选择的亚单层至一个单层厚度时终止原子束来确定厚度。

2. 发明授权

US6110840A Method of passivating the surface of a Si substrate 失效
标题翻译：钝化Si衬底表面的方法
公开(公告)号：US6110840A
公开(公告)日：2000-08-29
申请号：US24148
申请日：1998-02-17
申请人： Zhiyi Jimmy Yu , Corey D. Overgaard , Ravi Droopad , Jonathan K. Abrokwah , Jerald A. Hallmark
发明人： Zhiyi Jimmy Yu , Corey D. Overgaard , Ravi Droopad , Jonathan K. Abrokwah , Jerald A. Hallmark
IPC分类号： C23C14/02 , C23C14/16 , H01L21/285 , H01L21/306 , H01L21/31
CPC分类号： B82Y30/00 , C23C14/021 , C23C14/16 , H01L21/28518 , H01L21/02043
摘要： A method of passivating the surface of a Si wafer is disclosed including the steps of cleaning the surface of the Si wafer and depositing an alkaline earth metal on the clean surface at a wafer temperature in a range of approximately 400.degree. C. to 750.degree. C. The surface is monitored during deposition to detect a (4.times.2) surface reconstruction pattern indicating approximately a one-quarter monolayer of alkaline earth metal is formed. The wafer is annealed at a temperature in a range of 800.degree. C. to 900.degree. C. until the alkaline earth metal forms an alkaline earth metal silicide with a (2.times.1) surface pattern on the surface.
摘要翻译：公开了一种钝化Si晶片的表面的方法，包括以下步骤：在大约400℃至750℃的晶圆温度下清洁Si晶片的表面并在清洁表面上沉积碱土金属在沉积期间监测表面以检测（4×2）表面重建图案，其指示形成大约四分之一的碱土金属单层。将晶片在800℃至900℃的温度下进行退火，直到碱土金属在表面上形成具有（2x1）表面图案的碱土金属硅化物。

3. 发明授权

US08847280B2 Insulated gate field effect transistors 有权
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US08847280B2
公开(公告)日：2014-09-30
申请号：US13293910
申请日：2011-11-10
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/78 , H01L23/31 , H01L29/778 , H01L29/51 , H01L29/207
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。在半导体层上形成介电层。在电介质层上形成密封层并暴露于氧等离子体。在源 - 漏电极之间的电介质层上形成栅电极。电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。希望在密封层的上方设置另外的例如氮化硅的密封层。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

4. 发明授权

US08105925B2 Method for forming an insulated gate field effect device 有权
标题翻译：一种形成绝缘栅场效应器件的方法
公开(公告)号：US08105925B2
公开(公告)日：2012-01-31
申请号：US12182349
申请日：2008-07-30
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L21/26
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底（20）来获得改进的绝缘栅场效应器件（60），所述衬底（20）在所述衬底（20）上具有另外的半导体层（22），所述半导体层适于容纳所述沟道（230）所述器件（60）形成在所述半导体层（22）上形成的间隔开的源 - 漏电极（421,422）之间。在半导体层（22）上形成介电层（24）。密封层（28）形成在电介质层（24）上并暴露于氧等离子体（36）。在源漏电极（421,422）之间的电介质层（24）上形成栅电极（482）。电介质层（24）优选包含氧化镓（25）和/或氧化钆 - 氧化镓（26,27），氧等离子体（36）优选为电感耦合等离子体。期望地在密封层（28）的上方设置例如氮化硅的另外的密封层（44）。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

5. 发明申请

US20120056246A1 INSULATED GATE FIELD EFFECT TRANSISTORS 有权
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US20120056246A1
公开(公告)日：2012-03-08
申请号：US13293910
申请日：2011-11-10
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/78
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。在半导体层上形成介电层。在电介质层上形成密封层并暴露于氧等离子体。在源 - 漏电极之间的电介质层上形成栅电极。电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。希望在密封层的上方设置另外的例如氮化硅的密封层。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

6. 发明授权

US5606184A Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making 失效
$Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making$
标题翻译：异质结构场效应器件直接在通道层上具有难熔欧姆接触和制造方法
公开(公告)号：US5606184A
公开(公告)日：1997-02-25
申请号：US434867
申请日：1995-05-04
申请人： Jonathan K. Abrokwah , Jenn-Hwa Huang , William J. Ooms , Carl L. Shurboff , Jerald A. Hallmark
发明人： Jonathan K. Abrokwah , Jenn-Hwa Huang , William J. Ooms , Carl L. Shurboff , Jerald A. Hallmark
IPC分类号： H01L29/43 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/335 , H01L21/338 , H01L23/52 , H01L27/085 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/778 , H01L29/812 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66462 , H01L21/28575 , H01L27/085 , H01L29/0891 , H01L29/41766 , H01L29/452
摘要： A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).
摘要翻译：互补的III-V异质结构场效应器件包括用于向N型和P型器件提供触点（117,119）的相同难熔欧姆材料。此外，难熔欧姆接触（117,119）直接接触InGaAs沟道层（16）以提供改善的欧姆接触，尽管该结构包含有利的高铝成分阻挡层（18）和有利的GaAs覆盖层（ 20）。

7. 发明授权

US6113690A Method of preparing crystalline alkaline earth metal oxides on a Si substrate 失效
标题翻译：在Si衬底上制备结晶碱土金属氧化物的方法
公开(公告)号：US6113690A
公开(公告)日：2000-09-05
申请号：US93081
申请日：1998-06-08
申请人： Zhiyi Jimmy Yu , Jerald A. Hallmark , Jonathan K. Abrokwah , Corey D. Overgaard , Ravi Droopad
发明人： Zhiyi Jimmy Yu , Jerald A. Hallmark , Jonathan K. Abrokwah , Corey D. Overgaard , Ravi Droopad
IPC分类号： C30B23/02 , C30B25/02
CPC分类号： C30B23/02 , C30B29/16 , C30B29/22
摘要： A method of preparing crystalline alkaline earth metal oxides on a Si substrate wherein a Si substrate with amorphous silicon dioxide on a surface is provided. The substrate is heated to a temperature in a range of 700.degree. C. to 800.degree. C. and exposed to a beam of alkaline earth metal(s) in a molecular beam epitaxy chamber at a pressure within approximately a 10.sup.-9 -10.sup.-10 Torr range. During the molecular beam epitaxy the surface is monitored by RHEED technique to determine a conversion of the amorphous silicon dioxide to a crystalline alkaline earth metal oxide. Once the alkaline earth metal oxide is formed, additional layers of material, e.g. additional thickness of an alkaline earth metal oxide, single crystal ferroelectrics or high dielectric constant oxides on silicon for non-volatile and high density memory device applications.
摘要翻译：在Si衬底上制备结晶碱土金属氧化物的方法，其中提供了表面上具有无定形二氧化硅的Si衬底。将基底加热至700℃至800℃的温度，并在分子束外延室内以大约10-9-10℃的压力暴露于一束或多束碱土金属， 10乇范围。在分子束外延期间，通过RHEED技术监测表面以确定无定形二氧化硅向结晶碱土金属氧化物的转化。一旦形成碱土金属氧化物，可以使用另外的材料层。用于非易失性和高密度存储器件应用的碱土金属氧化物，单晶铁电体或硅上的高介电常数氧化物的附加厚度。

8. 发明申请

US20100025729A1 PASSIVATED III-V FIELD EFFECT STRUCTURE AND METHOD 有权
标题翻译：被动III-V场效应结构与方法
公开(公告)号：US20100025729A1
公开(公告)日：2010-02-04
申请号：US12182349
申请日：2008-07-30
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底（20）来获得改进的绝缘栅场效应器件（60），所述衬底（20）在所述衬底（20）上具有另外的半导体层（22），所述半导体层适于容纳所述沟道（230）所述器件（60）形成在所述半导体层（22）上形成的间隔开的源 - 漏电极（421,422）之间。在半导体层（22）上形成介电层（24）。密封层（28）形成在电介质层（24）上并暴露于氧等离子体（36）。在源漏电极（421,422）之间的电介质层（24）上形成栅电极（482）。电介质层（24）优选包含氧化镓（25）和/或氧化钆 - 氧化镓（26,27），氧等离子体（36）优选为电感耦合等离子体。期望地在密封层（28）的上方设置例如氮化硅的另外的密封层（44）。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

9. 发明授权

US06359294B1 Insulator-compound semiconductor interface structure 失效
标题翻译：绝缘体 - 复合半导体界面结构
公开(公告)号：US06359294B1
公开(公告)日：2002-03-19
申请号：US08812952
申请日：1997-03-04
申请人： Matthias Passlack , Jun Wang , Jonathan K. Abrokwah , Zhiyi Jimmy Yu
发明人： Matthias Passlack , Jun Wang , Jonathan K. Abrokwah , Zhiyi Jimmy Yu
IPC分类号： H01L2976
CPC分类号： H01L29/517 , H01L21/28158 , H01L21/28264 , H01L29/66462 , H01L29/802
摘要： An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.
摘要翻译：公开了一种绝缘体 - 化合物半导体界面结构，其包括具有半导体材料的隔离层的化合物半导体材料，该间隔层具有比位于化合物半导体材料的表面上的化合物半导体材料的带隙宽的带隙和位于化合物半导体材料的表面上的绝缘层间隔层。间隔层的最小和最大厚度由载波函数穿入间隔层和所需器件性能决定。在具体实施例中，界面结构形成在多晶片外延生产系统中，该系统包括连接有III-V生长室的传输和负载模块，并连接有绝缘体室。

10. 发明授权

US5904553A Fabrication method for a gate quality oxide-compound semiconductor structure 失效
标题翻译：栅极质量氧化物 - 半导体结构的制造方法
公开(公告)号：US5904553A
公开(公告)日：1999-05-18
申请号：US917119
申请日：1997-08-25
申请人： Matthias Passlack , Jonathan K. Abrokwah , Ravi Droopad , Brian Bowers
发明人： Matthias Passlack , Jonathan K. Abrokwah , Ravi Droopad , Brian Bowers
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , H01L21/316 , H01L21/3205 , H01L21/4763
CPC分类号： C23C16/45523 , C23C16/407 , C23C16/455 , C23C16/4551 , H01L21/31604
摘要： A method of fabricating a gate quality oxide-compound semiconductor structure includes forming an insulating Ga.sub.2 O.sub.3 layer on the surface of a compound semiconductor wafer structure by a supersonic gas jet containing gallium oxide molecules and oxygen. In a preferred embodiment, a III-V compound semiconductor wafer structure with an atomically ordered and chemically clean semiconductor surface is transferred from a semiconductor growth chamber into an insulator deposition chamber via an ultra high vacuum preparation chamber. Ga.sub.2 O.sub.3 deposition onto the surface of the wafer structure is initiated by a supersonic gas jet pulse and proceeds via optimization of pulse duration, speed of gas jet, mole fraction of gallium oxide molecules and oxygen atoms, and plasma energy.
摘要翻译：制造栅极质量氧化物半导体结构的方法包括通过含有氧化镓分子和氧的超音速气体射流在化合物半导体晶片结构的表面上形成绝缘Ga 2 O 3层。在优选实施例中，具有原子级和化学清洁的半导体表面的III-V族化合物半导体晶片结构经由超高真空准备室从半导体生长室转移到绝缘体沉积室中。通过超音速气体喷射脉冲引发晶片结构表面上的Ga 2 O 3沉积，并且经历脉冲持续时间，气体射流速度，氧化镓分子和氧原子的摩尔分数以及等离子体能量的优化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式