专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06410941B1 Reconfigurable systems using hybrid integrated circuits with optical ports 有权
标题翻译：使用具有光端口的混合集成电路的可重构系统
公开(公告)号：US06410941B1
公开(公告)日：2002-06-25
申请号：US09608931
申请日：2000-06-30
申请人： Michael G. Taylor , Charles W. Shanley , William J. Ooms
发明人： Michael G. Taylor , Charles W. Shanley , William J. Ooms
IPC分类号： H01L2715
CPC分类号： H01L27/15
摘要： A hybrid integrated circuit is provided that has a monocrystalline substrate such as silicon and a compound semiconductor layer such as gallium arsenide or indium phosphide. An optical communications port may be formed on the hybrid integrated circuit. Electrical equipment may be provided that includes electrical components. At least a given one of the components may be a hybrid integrated circuit. Data used for the operation of one of the given integrated circuit may be provided to the given integrated circuit through the optical communications port on that integrated circuit. The data may be loaded rapidly in real time due to the wide bandwidth of the optical communications port.
摘要翻译：提供了具有诸如硅的单晶衬底和诸如砷化镓或磷化铟的化合物半导体层的混合集成电路。可以在混合集成电路上形成光通信端口。可以提供包括电气部件的电气设备。至少给定的一个组件可以是混合集成电路。用于给定集成电路之一的操作的数据可以通过该集成电路上的光通信端口提供给给定的集成电路。由于光通信端口的宽带宽，数据可以实时快速加载。

2. 发明授权

US06262461B1 Method and apparatus for creating a voltage threshold in a FET 失效
标题翻译：用于在FET中产生电压阈值的方法和装置
公开(公告)号：US06262461B1
公开(公告)日：2001-07-17
申请号：US09102105
申请日：1998-06-22
申请人： Daniel S. Marshall , William J. Ooms , Jerald A. Hallmark , Yang Wang
发明人： Daniel S. Marshall , William J. Ooms , Jerald A. Hallmark , Yang Wang
IPC分类号： H01L31119
CPC分类号： H01L29/66568 , H01L29/4975 , H01L29/517 , H01L29/78 , H01L29/7838
摘要： A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.
摘要翻译：一种制造场效应晶体管的方法，包括在邻近表面的半导体衬底结构中掺杂连续覆盖层，以包括与源极区域间隔开的源极区域和漏极区域。高介电常数绝缘体层位于覆盖连续覆盖层的半导体衬底结构的表面上，以限定源区和漏区之间的栅极区。选择绝缘体层上的栅极接触以提供消耗绝缘体层下方的掺杂层的功函数差异。此外，掺杂层深度和剂量被设计成使得掺杂层通过栅极接触和半导体衬底的选择的功函数差耗尽在绝缘体层之下。

3. 发明授权

US6025735A Programmable switch matrix and method of programming 失效
标题翻译：可编程开关矩阵和编程方法
公开(公告)号：US6025735A
公开(公告)日：2000-02-15
申请号：US772735
申请日：1996-12-23
申请人： Robert M. Gardner , Jerald A. Hallmark , Daniel S. Marshall , William J. Ooms
发明人： Robert M. Gardner , Jerald A. Hallmark , Daniel S. Marshall , William J. Ooms
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/1736 , H03K19/17748 , H03K19/17756
摘要： A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an on-state. The ferroelectric transistor (32) functions as a nonvolatile latch and pass device to provide the electrical interconnect path that links multiple Configurable Logic Blocks (CLBs). The programming transistor (34) is selected to transfer a depolarizing voltage to the gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an off-state.
摘要翻译：现场可编程门阵列（FPGA）中的开关网络（22），其作为编程晶体管（34）和铁电晶体管（32）的组合工作。编程晶体管（34）被选择为将极化电压传递到铁电晶体管（32）的栅极端子，用于将铁电晶体管（32）编程为导通状态。铁电晶体管（32）用作非易失性锁存和通过装置，以提供链接多个可配置逻辑块（CLB）的电互连路径。编程晶体管（34）被选择为将去极化电压传递到铁电晶体管（32）的栅极端子，用于将铁电晶体管（32）编程为截止状态。

4. 发明授权

US5719088A Method of fabricating semiconductor devices with a passivated surface 失效
标题翻译：制造具有钝化表面的半导体器件的方法
公开(公告)号：US5719088A
公开(公告)日：1998-02-17
申请号：US556477
申请日：1995-11-13
申请人： Jenn-Hwa Huang , Mark Durlam , Marino J. Martinez , Ernie Schirmann , Saied N. Tehrani , William J. Ooms
发明人： Jenn-Hwa Huang , Mark Durlam , Marino J. Martinez , Ernie Schirmann , Saied N. Tehrani , William J. Ooms
IPC分类号： H01L21/285 , H01L21/311 , H01L21/335 , H01L23/485 , H01L21/44
CPC分类号： H01L29/66462 , H01L21/28587 , H01L21/31116 , H01L23/485 , H01L2924/0002
摘要： A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.
摘要翻译：制造具有钝化表面的半导体器件的方法包括在衬底上提供接触层以便限定电极间表面积。可以相对于彼此和基板和接触层选择性地蚀刻的第一层和绝缘层沉积在接触层和电极间表面区域上。分别选择性地蚀刻绝缘层和第一层以限定电极接触面积并暴露电极间表面积。暴露的电极间表面积在第一层蚀刻之前或期间被钝化。在与绝缘层邻接的电极接触区域中形成金属接触，以密封电极间表面积。

5. 发明授权

US5457405A Complementary logic recovered energy circuit 失效
标题翻译：互补逻辑恢复能量回路
公开(公告)号：US5457405A
公开(公告)日：1995-10-10
申请号：US364912
申请日：1994-12-27
申请人： William J. Ooms , Jerald A. Hallmark
发明人： William J. Ooms , Jerald A. Hallmark
IPC分类号： H03K19/00 , H03K19/096
CPC分类号： H03K19/0013 , H03K19/0019 , H03K19/0963
摘要： A circuit derives all power from a single clock input terminal and has no connections to separate power source or power sink terminals. The circuit configuration is applicable to many functions such as inverters, logic gates (NAND, NOR, etc.), and storage elements. When connected to form an inverter function, a current electrode of a first transistor is coupled to the clock input terminal and a control electrode is coupled to a signal input terminal while a second transistor has a current electrode coupled to the clock input terminal and a control electrode coupled the signal input terminal. Both transistors have a second current electrode coupled to an output of the inverter.
摘要翻译：电路从单个时钟输入端子获得所有电源，并且没有连接到单独的电源或电源端子。该电路配置适用于逆变器，逻辑门（NAND，NOR等）和存储元件等许多功能。当连接以形成反相器功能时，第一晶体管的电流电极耦合到时钟输入端子，并且控制电极耦合到信号输入端子，而第二晶体管具有耦合到时钟输入端子的电流电极和控制电极电极耦合信号输入端。两个晶体管都具有耦合到反相器的输出的第二电流电极。

6. 发明授权

US4125855A Integrated semiconductor crosspoint arrangement 失效
标题翻译：集成半导体交叉点布置
公开(公告)号：US4125855A
公开(公告)日：1978-11-14
申请号：US781790
申请日：1977-03-28
申请人： James A. Davis , William J. Ooms
发明人： James A. Davis , William J. Ooms
IPC分类号： H03K17/00 , H01L21/331 , H01L21/74 , H01L21/762 , H01L21/8224 , H01L23/535 , H01L27/082 , H01L27/102 , H01L29/08 , H01L29/73 , H03K17/62 , H03K17/66 , H03K17/68 , H04Q3/52 , H01L27/04
CPC分类号： H03K17/6221 , H01L21/743 , H01L21/762 , H01L23/535 , H01L27/0821 , H01L27/1022 , H03K17/668 , H03K17/68 , H04Q3/521 , H01L2924/0002 , H01L2924/3011
摘要： Symmetrical integrated transistors and drive circuitry provide low loss bilateral analog crosspoints for a switching matrix. Each crosspoint comprises a high performance PNP lateral transmission switching transistor and an associated NPN vertical drive transistor formed over a common n-type buried tub in a p-type substrate. Individual crosspoints, including the transmission transistor and the drive circuitry, are isolated by means of frame shaped p-type isolation regions lying outside the buried tub. The collector of the NPN drive transistor and the base of the PNP transmission transistor are ohmically connected by means of the buried tub. Accordingly, although the transmission transistor and the drive transistor are merged in a single isolation region, current drive to the PNP transistor is by means of the NPN transistor as a functionally independent device. The lateral PNP transistor comprises stripe shaped emitter and collector electrodes which are formed in a single step with the isolation region and the electrodes are of equal doping, size, and shape. Pluralities of such emitters and collectors which are respectively interconnected by surface metallizations may be utilized to increase the efficiency and the current carrying capacity of the transmission transistor.
摘要翻译：对称集成晶体管和驱动电路为开关矩阵提供低损耗的双向模拟交叉点。每个交叉点包括高性能PNP横向传输切换晶体管和形成在p型衬底中的公共n型埋置式桶上的相关联的NPN垂直驱动晶体管。包括传输晶体管和驱动电路在内的各个交叉点通过位于掩埋槽外部的框形的p型隔离区隔离开。 NPN驱动晶体管的集电极和PNP传输晶体管的基极通过埋地槽欧姆连接。因此，虽然传输晶体管和驱动晶体管合并在单个隔离区域中，但是通过作为功能无关的器件的NPN晶体管对PNP晶体管的电流驱动。横向PNP晶体管包括条形发射极和集电极，它们以隔离区形成一个单一步骤，并且电极具有相等的掺杂，尺寸和形状。分别通过表面金属化互连的这种发射器和集电器的多个可以用于提高传输晶体管的效率和载流能力。

7. 发明授权

US5767543A Ferroelectric semiconductor device having a layered ferroelectric structure 失效
标题翻译：具有分层铁电结构的铁电半导体器件
公开(公告)号：US5767543A
公开(公告)日：1998-06-16
申请号：US714715
申请日：1996-09-16
申请人： William J. Ooms , Daniel S. Marshall , Jerald A. Hallmark
发明人： William J. Ooms , Daniel S. Marshall , Jerald A. Hallmark
IPC分类号： H01L21/02 , H01L21/285 , H01L21/314 , H01L21/316 , H01L29/51 , H01L29/788 , G11C11/22
CPC分类号： H01L28/56 , H01L21/2855 , H01L21/28556 , H01L21/31691 , H01L29/516
摘要： A layered bismuth ferroelectric structure (12) and a method for forming the bismuth layered ferroelectric structure (12). A monolayer (12A) of bismuth is formed in intimate contact with a single crystalline semiconductor material (11). A layered ferroelectric material (12) is grown on the monolayer (12A) of bismuth such that the monolayer (12A) of bismuth becomes a part of the layered ferroelectric material (12). The ferroelectric material (12) forms a layered ferroelectric material which is not a pure perovskite, wherein the crystalline structure at the interface between the single crystalline semiconductor material (11) and the monolayer (12A) of bismuth are substantially the same.
摘要翻译：层状铋强电介质结构（12）和形成铋层状铁电体结构（12）的方法。形成与单晶半导体材料（11）紧密接触的铋单层（12A）。在铋的单层（12A）上生长分层的铁电材料（12），使得铋的单层（12A）成为层状铁电体（12）的一部分。铁电材料（12）形成不是纯钙钛矿的层状铁电体材料，其中在单晶半导体材料（11）和铋单层（12A）之间的界面处的晶体结构基本上相同。

8. 发明授权

US5039881A High speed, low power input buffer 失效
标题翻译：高速，低功耗输入缓冲器
公开(公告)号：US5039881A
公开(公告)日：1991-08-13
申请号：US370657
申请日：1989-06-23
申请人： William J. Ooms , Jerald A. Hallmark
发明人： William J. Ooms , Jerald A. Hallmark
IPC分类号： H03K19/018
CPC分类号： H03K19/01812
摘要： An input buffer includes an input circuit (80), a pair of complimentary outputs (52,54) and a differential ampliifer (12). The input buffer includes a pull-down diode (90) arranged in parallel with pull-up diodes (84, 86, and 88), coupled between the buffer input (82) and the differential amplifier input (32). Pull-up is achieved through the low impedance path of the pull-up diodes, eliminating a need for a high value resistor. Pull-down is achieved through the pull-down diode in series with a resistor (92). This arrangement provides high speed of operation, while reducing current consumption.
摘要翻译：输入缓冲器包括输入电路（80），一对互补输出（52,54）和差分放大器（12）。输入缓冲器包括与上拉二极管（84,86和88）并联布置的下拉二极管（90），耦合在缓冲器输入端（82）和差分放大器输入端（32）之间。通过上拉二极管的低阻抗路径实现上拉，无需使用高值电阻。通过与电阻（92）串联的下拉二极管实现下拉。这种布置提供高速操作，同时减少电流消耗。

9. 发明授权

US4325031A Divider with dual modulus prescaler for phase locked loop frequency synthesizer 失效
标题翻译：具有双模预分频器的分频器，用于锁相环频率合成器
公开(公告)号：US4325031A
公开(公告)日：1982-04-13
申请号：US121207
申请日：1980-02-13
申请人： William J. Ooms , Richard E. Barnett
发明人： William J. Ooms , Richard E. Barnett
IPC分类号： H03L7/18 , H03K23/66 , H03K21/36
CPC分类号： H03K23/667
摘要： A high frequency divider suitable for use in a frequency synthesizer using a dual modulus prescaler and two counters to achieve high speed and low current drain. The input signal is alternately divided by one of the two moduli in the prescaler and then alternately divided by one of the two counters. Each of the two counters is reset while the other is counting thereby reducing circuit complexity and increasing circuit speed.
摘要翻译：适用于使用双模预分频器和两个计数器的频率合成器实现高速和低电流消耗的高分频器。输入信号由预分频器中的两个模数中的一个交替分频，然后由两个计数器之一交替分频。两个计数器中的每一个被重置，而另一个计数器被计数，从而降低电路复杂性并提高电路速度。

10. 发明授权

US07342276B2 Method and apparatus utilizing monocrystalline insulator 有权
标题翻译：使用单晶绝缘子的方法和装置
公开(公告)号：US07342276B2
公开(公告)日：2008-03-11
申请号：US10861467
申请日：2004-06-07
申请人： William J. Ooms , Jerald A. Hallmark
发明人： William J. Ooms , Jerald A. Hallmark
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/19 , H01L31/113
CPC分类号： H01L28/55 , H01L21/28194 , H01L21/28202 , H01L21/31691 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive element and substantially lattice matched to the semiconductor material.
摘要翻译：一种半导体器件，包括：半导体材料; 导电元件; 以及设置在半导体材料和导电元件之间并基本上与半导体材料晶格匹配的基本单晶绝缘体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式