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1. 发明申请

US20090085073A1 MOSFET STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译： MOSFET结构及其制造方法
公开(公告)号：US20090085073A1
公开(公告)日：2009-04-02
申请号：US11864274
申请日：2007-09-28
申请人： Ravindranath Droopad , Matthias Passlack
发明人： Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28264 , H01L29/517
摘要： A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.
摘要翻译：形成化合物半导体MOSFET结构的部分（10）的方法包括：形成化合物半导体层结构（14）和覆盖其上的氧化物层（20）。形成化合物半导体结构（14）包括形成至少一个沟道材料（16）和覆盖至少一个沟道材料的III族富集表面终止层（18）。形成氧化物层（20）包括形成氧化物层以覆盖III族富集表面终止层，并且包括（a）基本上一致地沉积（a（i））三元氧化物和（（ii））比三元氧化物更复杂的氧化物和（b）使用（b（i））三元氧化物和（b（ii））中的至少一种沉积氧化物分子，其比三元氧化物。

2. 发明授权

US07105886B2 High K dielectric film 有权
标题翻译：高K电介质膜
公开(公告)号：US07105886B2
公开(公告)日：2006-09-12
申请号：US10895552
申请日：2004-07-21
申请人： Ravindranath Droopad
发明人： Ravindranath Droopad
IPC分类号： A01L29/76
CPC分类号： H01L21/28194 , H01L21/02192 , H01L21/02194 , H01L21/02269 , H01L21/28273 , H01L21/31604 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A dielectric layer comprised of lanthanum, lutetium, and oxygen that is formed between two conductors or a conductor and a substrate. In one embodiment, the dielectric layer is formed over the substrate without the need for an additional interfacial layer. In another embodiment, the dielectric layer is graded with respect to the lanthanum or lutetium content or in the alternative, may include aluminum. In yet another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer or between both the conductor and substrate and the dielectric layer. The dielectric layer is preferably formed by molecular beam epitaxy, but can also be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.
摘要翻译：由镧，镥和氧构成的介电层，其形成在两个导体或导体与基板之间。在一个实施例中，介电层形成在衬底上，而不需要额外的界面层。在另一个实施方案中，介电层相对于镧或镥含量分级，或者替代地，可以包括铝。在另一个实施例中，在导体或衬底与电介质层之间或在导体和衬底与电介质层之间形成绝缘层。电介质层优选通过分子束外延形成，但也可以通过原子层化学气相沉积，物理气相沉积，有机金属化学气相沉积或脉冲激光沉积形成。

3. 发明申请

US20060030098A1 Method of forming an oxide layer on a compound semiconductor structure 有权
标题翻译：在化合物半导体结构上形成氧化物层的方法
公开(公告)号：US20060030098A1
公开(公告)日：2006-02-09
申请号：US11239749
申请日：2005-09-30
申请人： Ravindranath Droopad , Matthias Passlack
发明人： Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L21/8238
CPC分类号： H01L21/02266 , H01L21/02175 , H01L21/022 , H01L21/28264 , H01L21/31604 , H01L29/20 , H01L29/513 , H01L29/78
摘要： A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.
摘要翻译：在具有第一表面的支撑半导体结构上形成电介质层结构的方法包括：提供第一氧化物束; 使用第一氧化物束在支撑半导体结构的第一表面上沉积第一层氧化物，其中所述第一氧化物层具有第二表面; 终止第一氧化物束，并且同时提供第二氧化物束，金属梁和氧束，其中所述第一和第二氧化物束是分离的和不同的氧化物束; 以及使用所述第二氧化物束，所述金属束和所述氧束将所述第二表面的氧化物沉积在所述第二表面上。

4. 发明授权

US06693033B2 Method of removing an amorphous oxide from a monocrystalline surface 有权
标题翻译：从单晶表面除去无定形氧化物的方法
公开(公告)号：US06693033B2
公开(公告)日：2004-02-17
申请号：US09983854
申请日：2001-10-26
申请人： John L. Edwards, Jr. , Yi Wei , Dirk C. Jordan , Xiaoming Hu , James Bradley Craigo , Ravindranath Droopad , Zhiyi Yu , Alexander A. Demkov
发明人： John L. Edwards, Jr. , Yi Wei , Dirk C. Jordan , Xiaoming Hu , James Bradley Craigo , Ravindranath Droopad , Zhiyi Yu , Alexander A. Demkov
IPC分类号： H01L2120
CPC分类号： C30B25/18 , C30B33/00 , H01L21/02197 , H01L21/02299 , H01L21/02381 , H01L21/02433 , H01L21/02439 , H01L21/02472 , H01L21/02488 , H01L21/02505 , H01L21/02507 , H01L21/02513 , H01L21/02543 , H01L21/02546 , H01L21/02557 , H01L21/0256 , H01L21/31111 , H01L21/31691 , H01L21/8252 , H01L21/8258 , H01L27/0605 , H01L27/15 , H01L33/16 , H01L33/30
摘要： A method of removing an amorphous oxide from a surface of a monocrystalline substrate is provided. The method includes depositing a passivation material overlying the amorphous oxide. The monocrystalline substrate is then heated so that the amorphous oxide layer decomposes into at least one volatile species that is liberated from the surface.
摘要翻译：提供了从单晶衬底的表面去除非晶氧化物的方法。该方法包括沉积覆盖无定形氧化物的钝化材料。然后加热单晶衬底，使得无定形氧化物层分解成从表面释放出的至少一种挥发性物质。

5. 发明授权

US06319730B1 Method of fabricating a semiconductor structure including a metal oxide interface 有权
标题翻译：制造包括金属氧化物界面的半导体结构的方法
公开(公告)号：US06319730B1
公开(公告)日：2001-11-20
申请号：US09354522
申请日：1999-07-15
申请人： Jamal Ramdani , Ravindranath Droopad , Zhiyi Yu
发明人： Jamal Ramdani , Ravindranath Droopad , Zhiyi Yu
IPC分类号： H01L2100
CPC分类号： H01L21/31691
摘要： A method for fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12); forming amorphous silicon dioxide (14) on the surface (12) of the silicon substrate (10); providing a metal oxide (18) on the amorphous silicon dioxide (14); heating the semiconductor structure to form an interface comprising a seed layer (20) adjacent the surface (12) of the silicon substrate (10); and forming one or more layers of a high dielectric constant oxide (22) on the seed layer (20).
摘要翻译：一种制造半导体结构的方法，包括以下步骤：提供具有表面（12）的硅衬底（10）; 在所述硅衬底（10）的表面（12）上形成无定形二氧化硅（14）; 在所述无定形二氧化硅（14）上提供金属氧化物（18）; 加热半导体结构以形成包括邻近硅衬底（10）的表面（12）的晶种层（20）的界面; 以及在种子层（20）上形成一层或多层高介电常数氧化物（22）。

6. 发明授权

US6159834A Method of forming a gate quality oxide-compound semiconductor structure 失效
标题翻译：形成栅极氧化物半导体结构的方法
公开(公告)号：US6159834A
公开(公告)日：2000-12-12
申请号：US22595
申请日：1998-02-12
申请人： Zhiyi (Jimmy) Yu , Matthias Passlack , Brian Bowers , Corey Daniel Overgaard , Ravindranath Droopad , Jonathan Kwadwo Abrokwah
发明人： Zhiyi (Jimmy) Yu , Matthias Passlack , Brian Bowers , Corey Daniel Overgaard , Ravindranath Droopad , Jonathan Kwadwo Abrokwah
IPC分类号： H01L21/28 , H01L21/316 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28264 , H01L21/31604 , H01L21/31666
摘要： A gate quality oxide-compound semiconductor structure (10) is formed by the steps of providing a III-V compound semiconductor wafer structure (13) with an atomically ordered and chemically clean semiconductor surface in an ultra high vacuum (UHV) system (20), directing a molecular beam (26) of gallium oxide onto the surface of the wafer structure to initiate the oxide deposition, and providing a second beam (28) of atomic oxygen to form a Ga.sub.2 O.sub.3 layer (14) with low defect density on the surface of the wafer structure. The second beam of atomic oxygen is supplied upon completion of the first 1-2 monolayers of Ga.sub.2 O.sub.3. The molecular beam of gallium oxide is provided by thermal evaporation from a crystalline Ga.sub.2 O.sub.3 or gallate source, and the atomic beam of oxygen is provided by either RF or microwave plasma discharge, thermal dissociation, or a neutral electron stimulated desorption atom source.
摘要翻译：通过在超高真空（UHV）系统（20）中提供具有原子级和化学清洁的半导体表面的III-V化合物半导体晶片结构（13）的步骤形成栅极质量氧化物 - 化合物半导体结构（10）将氧化镓的分子束（26）引导到晶片结构的表面上以引发氧化物沉积，以及提供原子氧的第二光束（28）以在表面上形成具有低缺陷密度的Ga 2 O 3层（14）的晶片结构。当第一个1-2单层的Ga2O3完成时，第二个原子氧束被提供。通过从结晶Ga 2 O 3或没食子酸酯源的热蒸发提供氧化镓的分子束，并且氧原子束由RF或微波等离子体放电，热解离或中性电子刺激的解吸原子源提供。

7. 发明申请

US20120056246A1 INSULATED GATE FIELD EFFECT TRANSISTORS 有权
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US20120056246A1
公开(公告)日：2012-03-08
申请号：US13293910
申请日：2011-11-10
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/78
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。在半导体层上形成介电层。在电介质层上形成密封层并暴露于氧等离子体。在源 - 漏电极之间的电介质层上形成栅电极。电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。希望在密封层的上方设置另外的例如氮化硅的密封层。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

8. 发明授权

US07682912B2 III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same 有权
标题翻译： III-V族化合物半导体器件，其具有与沟道电荷极性相反的电荷的存取区域中的表面层及其制造方法
公开(公告)号：US07682912B2
公开(公告)日：2010-03-23
申请号：US11554859
申请日：2006-10-31
申请人： Matthias Passlack , Ravindranath Droopad , Karthik Rajagopalan
发明人： Matthias Passlack , Ravindranath Droopad , Karthik Rajagopalan
IPC分类号： H01L21/336
CPC分类号： H01L29/66924 , H01L29/2003
摘要： A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.
摘要翻译：一种形成III-V族化合物半导体结构（10）的方法包括：提供一种III-V族化合物半导体衬底，该III-V族化合物半导体衬底包括半导体衬底（12），该半绝缘衬底具有形成在其上的至少一个外延层，并且还具有覆盖所述至少一个外延层。形成在半绝缘衬底上的至少一个外延层包括适于用于形成III-V族化合物半导体MOSFET器件的沟道的外延结构，其中，具有第一极性的沟道（30）。该方法还包括在栅极绝缘体的表面形成电荷层（22），电荷层具有第二极性，其中第二极性与第一极性相反。

9. 发明授权

US07105866B2 Heterojunction tunneling diodes and process for fabricating same 有权
标题翻译：异质结隧道二极管及其制造方法
公开(公告)号：US07105866B2
公开(公告)日：2006-09-12
申请号：US10911624
申请日：2004-08-05
申请人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
发明人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
IPC分类号： H01L29/861
CPC分类号： H01L29/882 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02505 , H01L21/02521 , H01L21/8258 , H01L27/0605
摘要： High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
摘要翻译：通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

10. 发明授权

US07067856B2 Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same 有权
公开(公告)号：US07067856B2
公开(公告)日：2006-06-27
申请号：US10768108
申请日：2004-02-02
申请人： Jamal Ramdani , Ravindranath Droopad , Lyndee L. Hilt , Kurt Williamson Eisenbeiser
发明人： Jamal Ramdani , Ravindranath Droopad , Lyndee L. Hilt , Kurt Williamson Eisenbeiser
IPC分类号： H01L31/072
CPC分类号： H01S5/0261 , C30B25/18 , H01L21/02381 , H01L21/02433 , H01L21/02439 , H01L21/02472 , H01L21/02488 , H01L21/02505 , H01L21/02507 , H01L21/02513 , H01L21/02521 , H01L21/02543 , H01L21/02546 , H01L21/02557 , H01L21/0256 , H01L21/31691 , H01L21/8252 , H01L21/8258 , H01L27/0605 , H01L27/15 , H01L33/16 , H01L33/30 , H01L2924/0002 , H01S5/021 , H01L2924/00
摘要： High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

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