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1. 发明申请

US20080035992A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080035992A1
公开(公告)日：2008-02-14
申请号：US11836383
申请日：2007-08-09
申请人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7828
摘要： This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer.A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.
摘要翻译：该半导体器件包括形成在第一导电类型的漏极层上的第一导电类型的漂移层和电连接到漏极层的漏电极。在漂移层的表面上形成第二导电类型的半导体基底层，并且在半导体基底层中进一步形成第一导电类型的源极区。源电极电连接到源区和半导体基层。多个栅电极通过栅极绝缘膜形成，使得半导体基底层可以被栅电极夹持。被栅电极夹持的半导体基底层的宽度为0.3微米以下。

2. 发明授权

US5793065A Insulated-gate thyristor 失效
公开(公告)号：US5793065A
公开(公告)日：1998-08-11
申请号：US483325
申请日：1995-06-07
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L29/423 , H01L29/745 , H01L29/749 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

3. 发明授权

US06236069B1 Insulated-gate thyristor 失效
标题翻译：绝缘栅晶闸管
公开(公告)号：US06236069B1
公开(公告)日：2001-05-22
申请号：US09102360
申请日：1998-06-23
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L2974
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
摘要翻译：本文公开了一种绝缘栅极晶闸管，其包括第一导电类型的基极层，具有第一和第二主表面，形成在基底层的第一主表面中的第一导电类型的第一主电极区域，第二导电类型的第二主表面形成在基底层的第二主表面的第二导电类型的主电极区域，至少一对从第一主电极区域延伸到基底层中并且彼此相对并间隔开预定的凹槽距离，形成在沟槽内的绝缘栅电极，以及用于从基层释放第二导电类型的载流子的关断绝缘栅晶体管结构。

4. 发明授权

US5464994A Insulated-gate thyristor 失效
标题翻译：绝缘栅晶闸管
公开(公告)号：US5464994A
公开(公告)日：1995-11-07
申请号：US291754
申请日：1994-08-16
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L29/423 , H01L29/745 , H01L29/749 , H01L29/74
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
摘要翻译：本文公开了一种绝缘栅极晶闸管，其包括第一导电类型的基极层，具有第一和第二主表面，形成在基底层的第一主表面中的第一导电类型的第一主电极区域，第二导电类型的第二主表面形成在基底层的第二主表面的第二导电类型的主电极区域，至少一对从第一主电极区域延伸到基底层中并且彼此相对并间隔开预定的凹槽距离，形成在沟槽内的绝缘栅电极，以及用于从基层释放第二导电类型的载流子的关断绝缘栅晶体管结构。

5. 发明授权

US5381026A Insulated-gate thyristor 失效
公开(公告)号：US5381026A
公开(公告)日：1995-01-10
申请号：US760344
申请日：1991-09-16
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L29/423 , H01L29/745 , H01L29/749 , H01L27/08 , H01L29/74
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

6. 发明授权

US5428228A Method of operating thyristor with insulated gates 失效
标题翻译：用绝缘栅极操作晶闸管的方法
公开(公告)号：US5428228A
公开(公告)日：1995-06-27
申请号：US164756
申请日：1993-12-10
申请人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
发明人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
IPC分类号： H01L27/06 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/747
CPC分类号： H01L27/0617 , H01L29/7436 , H01L29/7455 , H01L29/749
摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.
摘要翻译：具有绝缘栅极的晶闸管包括关断和导通MOSFET。导通MOSFET具有采用p型基极作为沟道并在n型基极和n型发射极上延伸的导通栅极。关断MOSFET具有形成在p型基极层中的n型漏极和源极层，以及在漏极和源极层上延伸的截止栅极。 n型漏极层经由漏电极与p型基极层短路。在n型发射极层附近形成漏电极。当晶闸管关断时，第一电压被施加到导通栅极，并且第二电压被施加到关断栅极，同时第一电压被施加到导通栅极。在第二电压的施加持续预定时间段之后，停止向导通门施加第一电压。通过这种操作，即使使用大电流，晶闸管也可以关闭。

7. 发明授权

US5463231A Method of operating thyristor with insulated gates 失效
公开(公告)号：US5463231A
公开(公告)日：1995-10-31
申请号：US353385
申请日：1994-12-02
申请人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
发明人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
IPC分类号： H01L27/06 , H01L29/74 , H01L29/745 , H01L29/749 , H01L31/111
CPC分类号： H01L27/0617 , H01L29/7436 , H01L29/7455 , H01L29/749
摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

8. 发明授权

US08008715B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08008715B2
公开(公告)日：2011-08-30
申请号：US12185630
申请日：2008-08-04
申请人： Yusuke Kawaguchi , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
发明人： Yusuke Kawaguchi , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/7811
摘要： There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.
摘要翻译：提供一种半导体器件，包括：第一导电类型的第一半导体层; 设置在第一导电类型的第一半导体层上的第二导电类型的第二半导体层; 选择性地设置在第二导电类型的第二半导体层的前表面部分上的第一导电类型的半导体区域; 设置成与半导体区域的表面接触的第一主电极; 设置在第一导电类型的第一半导体层的一侧的第二主电极，与设置有第二导电类型的第二半导体层的表面相对的一侧; 围绕设置有半导体区域的元件区域设置在第二导电类型的第二半导体层上的栅极布线; 穿过第二导电类型的第二半导体层的沟槽到达第一导电类型的第一半导体层，并且还在元件区域和栅极布线之下延伸; 设置在所述元件区域的所述沟槽内部的栅电极，其间插入有栅极绝缘膜; 以及栅极引线部分，其设置在栅极布线下方的沟槽内部，栅极绝缘膜介于其间并与栅极布线和栅电极接触。

9. 发明申请

US20090032875A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090032875A1
公开(公告)日：2009-02-05
申请号：US12185630
申请日：2008-08-04
申请人： Yusuke KAWAGUCHI , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
发明人： Yusuke KAWAGUCHI , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/7811
摘要： There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.
摘要翻译：提供一种半导体器件，包括：第一导电类型的第一半导体层; 设置在第一导电类型的第一半导体层上的第二导电类型的第二半导体层; 选择性地设置在第二导电类型的第二半导体层的前表面部分上的第一导电类型的半导体区域; 设置成与所述半导体区域的表面接触的第一主电极; 设置在第一导电类型的第一半导体层的一侧的第二主电极，与设置有第二导电类型的第二半导体层的表面相对的一侧; 围绕设置有半导体区域的元件区域设置在第二导电类型的第二半导体层上的栅极布线; 穿过第二导电类型的第二半导体层的沟槽到达第一导电类型的第一半导体层，并且还在元件区域和栅极布线之下延伸; 设置在所述元件区域的所述沟槽内部的栅电极，其间插入有栅极绝缘膜; 以及栅极引线部分，其设置在栅极布线下方的沟槽内部，栅极绝缘膜介于其间并与栅极布线和栅电极接触。

10. 发明授权

US5554862A Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US5554862A
公开(公告)日：1996-09-10
申请号：US183364
申请日：1994-01-19
申请人： Ichiro Omura , Mitsuhiko Kitagawa , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Ichiro Omura , Mitsuhiko Kitagawa , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/745 , H01L29/749 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/749
摘要： In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.
摘要翻译：在功率半导体器件中，在p发射极层上形成n基极。在n基层上，横向形成p基层，n发射极层和高浓度p层。在p基层中，n型源层与n型发射极层隔开规定的距离。在n-发射极层中，与高浓度p层隔开规定的距离形成p源层。在由n源层和n发射极层夹在的区域上经由第一栅极绝缘膜形成第一栅电极。在由高浓度p层和p源层夹着的区域上经由第二栅极绝缘膜形成第二栅电极。在p发射极层上形成第一主电极。第二主电极形成为与p基层，n源层和p源层接触。

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