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1. 发明申请

US20080035992A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080035992A1
公开(公告)日：2008-02-14
申请号：US11836383
申请日：2007-08-09
申请人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7828
摘要： This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer.A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.
摘要翻译：该半导体器件包括形成在第一导电类型的漏极层上的第一导电类型的漂移层和电连接到漏极层的漏电极。在漂移层的表面上形成第二导电类型的半导体基底层，并且在半导体基底层中进一步形成第一导电类型的源极区。源电极电连接到源区和半导体基层。多个栅电极通过栅极绝缘膜形成，使得半导体基底层可以被栅电极夹持。被栅电极夹持的半导体基底层的宽度为0.3微米以下。

2. 发明授权

US08049270B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08049270B2
公开(公告)日：2011-11-01
申请号：US11924175
申请日：2007-10-25
申请人： Miwako Akiyama , Akio Nakagawa , Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Akio Nakagawa , Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi
IPC分类号： H01L29/732
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.
摘要翻译：该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。

3. 发明申请

US20070194375A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070194375A1
公开(公告)日：2007-08-23
申请号：US11674337
申请日：2007-02-13
申请人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
发明人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译：该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。端接层形成为具有大于基底层的结深度的结深度。

4. 发明授权

US07485921B2 Trench gate type MOS transistor semiconductor device 失效
标题翻译：沟槽型MOS晶体管半导体器件
公开(公告)号：US07485921B2
公开(公告)日：2009-02-03
申请号：US11674337
申请日：2007-02-13
申请人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
发明人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译：该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。端接层形成为具有大于基底层的结深度的结深度。

5. 发明申请

US20070262410A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070262410A1
公开(公告)日：2007-11-15
申请号：US11742133
申请日：2007-04-30
申请人： Syotaro Ono , Yusuke Kawaguchi , Yoshihiro Yamaguchi , Miwako Akiyama
发明人： Syotaro Ono , Yusuke Kawaguchi , Yoshihiro Yamaguchi , Miwako Akiyama
IPC分类号： H01L29/00
CPC分类号： H01L29/872 , H01L27/0727 , H01L29/66143 , H01L29/8725
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type, a plurality of trenches provided on a major surface side of the semiconductor layer, an insulating film provided on an inner wall surface and on top of the trench, a conductive material surrounded by the insulating film and filling the trench, a first semiconductor region of a second conductivity type provided between the trenches, a second semiconductor region of the first conductivity type provided in a surface portion of the first semiconductor region, a mesa of the semiconductor layer provided between the trenches of a Schottky barrier diode region adjacent to a transistor region including the first semiconductor region and the second semiconductor region, a control electrode connected to the conductive material filling the trench of the transistor region and a main electrode provided in contact with a surface of the first semiconductor region, the second semiconductor region, a surface of the mesa and a part of the conductive material filling the trench of the Schottky barrier diode region. The part is exposed through the insulating film.
摘要翻译：半导体器件包括：第一导电类型的半导体层，设置在半导体层的主表面侧的多个沟槽，设置在内壁表面上和沟槽顶部上的绝缘膜，由绝缘膜并填充沟槽，设置在沟槽之间的第二导电类型的第一半导体区域，设置在第一半导体区域的表面部分中的第一导电类型的第二半导体区域，设置在第一半导体区域之间的半导体层的台面与包括第一半导体区域和第二半导体区域的晶体管区域相邻的肖特基势垒二极管区域的沟槽，连接到填充晶体管区域的沟槽的导电材料的控制电极和与第一半导体区域和第二半导体区域的表面接触的主电极第一半导体区域，第二半导体区域，台面的表面以及填充肖特基势垒二极管区域的沟槽的导电材料的一部分。该部件通过绝缘膜曝光。

6. 发明授权

US08410546B2 Semiconductor device and DC-DC converter 有权
标题翻译：半导体器件和DC-DC转换器
公开(公告)号：US08410546B2
公开(公告)日：2013-04-02
申请号：US12408056
申请日：2009-03-20
申请人： Yusuke Kawaguchi , Miwako Akiyama , Yoshihiro Yamaguchi , Nobuyuki Sato , Shigeaki Hayase
发明人： Yusuke Kawaguchi , Miwako Akiyama , Yoshihiro Yamaguchi , Nobuyuki Sato , Shigeaki Hayase
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/42368 , H01L29/66666 , H01L29/7803 , H01L29/7813 , H01L29/7827 , H02M3/1588 , Y02B70/1466
摘要： A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
摘要翻译：半导体器件包括：第一导电类型的半导体衬底; 设置在所述半导体衬底中的半导体区域; 形成在半导体区域中的第一沟槽; 形成在所述半导体衬底中的第二沟槽; 设置在所述第一沟槽中的沟槽栅电极; 以及设置在第二沟槽中的沟槽源电极。沟槽源电极的形状像条纹，并通过其纵向部分连接到源电极。

7. 发明授权

US07872308B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07872308B2
公开(公告)日：2011-01-18
申请号：US12332260
申请日：2008-12-10
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0869 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.
摘要翻译：半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层设置在第一半导体层的主表面上并且具有比第一半导体层的杂质浓度低的第二半导体层; 设置在第二半导体层上的第二导电类型的第三半导体层; 选择性地设置在第三半导体层上的第一导电类型的第四半导体层; 设置在穿过所述第三半导体层并到达所述第二半导体层的沟槽中的栅电极; 与所述第四半导体层接触的第一主电极，并且通过设置成在所述连续的栅电极之间穿过所述第四半导体层的接触槽使所述第三半导体层接触; 设置在与所述第一半导体层的主表面相反的表面上的第二主电极; 以及第二导电类型的第五半导体层，设置在与所述接触槽下方的部分对应的所述第二半导体层的内部。第五半导体层的最上部与第三半导体层接触，第五半导体层的最下部分的杂质浓度比第五半导体层中的其他部分杂质浓度高，位于第二半导体层中，第一半导体层，第五半导体层从最上部到最下部较窄。

8. 发明申请

US20080116512A1 SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080116512A1
公开(公告)日：2008-05-22
申请号：US11943181
申请日：2007-11-20
申请人： Yusuke Kawaguchi , Miwako Akiyama , Yoshihiro Yamaguchi
发明人： Yusuke Kawaguchi , Miwako Akiyama , Yoshihiro Yamaguchi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a first conductivity type layer and a second conductivity type layer, which are alternately and repeatedly positioned, adjacent to each other, in a column-like fashion on a first conductivity type substrate. The balance of the net charge amount of the impurity between the first conductivity type layer formed under a second conductivity type base layer in the termination region of the semiconductor device and the second conductivity type layer adjacent to the first conductivity type layer is imbalanced in comparison to the balance of the net charge amount of the impurity between the first conductivity type layer in the device-forming region of the semiconductor device and the second conductivity type layer adjacent to the first conductivity type layer.
摘要翻译：半导体器件包括在第一导电类型衬底上以列状方式彼此相邻地交替地和重复地定位的第一导电类型层和第二导电类型层。半导体器件的端接区域内的第二导电型基底层下方形成的第一导电型层与第一导电型层相邻的第二导电型层之间的杂质的净电荷量的平衡与第半导体器件的器件形成区域中的第一导电型层与第一导电型层相邻的第二导电型层之间的杂质的净电荷量的平衡。

9. 发明授权

US08169023B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08169023B2
公开(公告)日：2012-05-01
申请号：US12502759
申请日：2009-07-14
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/41766
摘要： An impurity concentration profile in a vertical direction of a p type base contact layer of a power semiconductor device has a two-stage configuration. In other word, the impurity concentration profile is highest at an upper face of the p type base contact layer, has a local minimum value at a position other than the upper face and a lower face of the base contact layer, and has a local maximum value at a position lower than the position of the local minimum value.
摘要翻译：功率半导体器件的p型基极接触层的垂直方向的杂质浓度分布具有两级结构。换句话说，杂质浓度分布在p型基底接触层的上表面处最高，在基底接触层的上表面和下表面以外的位置处具有局部最小值，并且具有局部最大值在低于局部最小值的位置的位置处的值。

10. 发明授权

US08106454B2 Power semiconductor device and method for manufacturing same 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08106454B2
公开(公告)日：2012-01-31
申请号：US12266331
申请日：2008-11-06
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/00
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66734 , H01L29/7813
摘要： A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant.
摘要翻译：垂直功率半导体器件包括形成在电池部分和终端部分中的第一导电类型的第一半导体层，围绕电池部分的端接部分，形成在第一半导体层上的第二导电类型的第二半导体层单元部分，部分地形成在第二半导体层上的第一导电类型的第三半导体层和形成在终端部分中的第一半导体层上的第二导电类型的保护环层。保护环层中的净杂质浓度一般是倾斜的，在其下侧相对较高，而在其上侧相对较低。或者，保护环层中的净杂质浓度恒定。

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