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1. 发明授权

US5381026A Insulated-gate thyristor 失效
公开(公告)号：US5381026A
公开(公告)日：1995-01-10
申请号：US760344
申请日：1991-09-16
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L29/423 , H01L29/745 , H01L29/749 , H01L27/08 , H01L29/74
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

2. 发明授权

US5554862A Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US5554862A
公开(公告)日：1996-09-10
申请号：US183364
申请日：1994-01-19
申请人： Ichiro Omura , Mitsuhiko Kitagawa , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Ichiro Omura , Mitsuhiko Kitagawa , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/745 , H01L29/749 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/749
摘要： In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.
摘要翻译：在功率半导体器件中，在p发射极层上形成n基极。在n基层上，横向形成p基层，n发射极层和高浓度p层。在p基层中，n型源层与n型发射极层隔开规定的距离。在n-发射极层中，与高浓度p层隔开规定的距离形成p源层。在由n源层和n发射极层夹在的区域上经由第一栅极绝缘膜形成第一栅电极。在由高浓度p层和p源层夹着的区域上经由第二栅极绝缘膜形成第二栅电极。在p发射极层上形成第一主电极。第二主电极形成为与p基层，n源层和p源层接触。

3. 发明授权

US06236069B1 Insulated-gate thyristor 失效
标题翻译：绝缘栅晶闸管
公开(公告)号：US06236069B1
公开(公告)日：2001-05-22
申请号：US09102360
申请日：1998-06-23
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L2974
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
摘要翻译：本文公开了一种绝缘栅极晶闸管，其包括第一导电类型的基极层，具有第一和第二主表面，形成在基底层的第一主表面中的第一导电类型的第一主电极区域，第二导电类型的第二主表面形成在基底层的第二主表面的第二导电类型的主电极区域，至少一对从第一主电极区域延伸到基底层中并且彼此相对并间隔开预定的凹槽距离，形成在沟槽内的绝缘栅电极，以及用于从基层释放第二导电类型的载流子的关断绝缘栅晶体管结构。

4. 发明授权

US5464994A Insulated-gate thyristor 失效
标题翻译：绝缘栅晶闸管
公开(公告)号：US5464994A
公开(公告)日：1995-11-07
申请号：US291754
申请日：1994-08-16
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L29/423 , H01L29/745 , H01L29/749 , H01L29/74
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
摘要翻译：本文公开了一种绝缘栅极晶闸管，其包括第一导电类型的基极层，具有第一和第二主表面，形成在基底层的第一主表面中的第一导电类型的第一主电极区域，第二导电类型的第二主表面形成在基底层的第二主表面的第二导电类型的主电极区域，至少一对从第一主电极区域延伸到基底层中并且彼此相对并间隔开预定的凹槽距离，形成在沟槽内的绝缘栅电极，以及用于从基层释放第二导电类型的载流子的关断绝缘栅晶体管结构。

5. 发明授权

US5793065A Insulated-gate thyristor 失效
公开(公告)号：US5793065A
公开(公告)日：1998-08-11
申请号：US483325
申请日：1995-06-07
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L29/423 , H01L29/745 , H01L29/749 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

6. 发明授权

US5689121A Insulated-gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US5689121A
公开(公告)日：1997-11-18
申请号：US480389
申请日：1995-06-07
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

7. 发明授权

US5329142A Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure 失效
标题翻译：具有注入增强晶体管结构的自熄绝缘栅功率半导体器件
公开(公告)号：US5329142A
公开(公告)日：1994-07-12
申请号：US925870
申请日：1992-08-07
申请人： Mitsuhiko Kitagawa , Ichiro Omura
发明人： Mitsuhiko Kitagawa , Ichiro Omura
IPC分类号： H01L29/74 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78 , H01L21/36 , H01L21/74
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： A self turn-off power semiconductor device includes a P type emitter layer, a high resistive N type base layer, a P type base layer and a MOS channel structure for injecting electrons into the N type base layer. A series of trench-like grooves are formed in the top surface of a substrate constituting the N type base layer at a constant interval. Insulated gate electrodes are buried in these grooves. The injection efficiency of electrons into the base layer is enhanced by locally controlling the flow of holes in the N type base layer. Controlling the flow of holes is achieved by specifically arranging the width of a hole-bypass path among the grooves, the trench width and the placement distance of the grooves, thereby causing the accumulation of carriers to increase in the base layer to decrease the on-resistance of the device.
摘要翻译：自关断功率半导体器件包括用于将电子注入到N型基极层中的P型发射极层，高电阻N型基极层，P型基极层和MOS沟道结构。在构成N型基底层的基板的上表面中以一定间隔形成一系列沟槽状的沟槽。绝缘栅电极被埋在这些槽中。通过局部地控制N型基底层中的空穴流动，提高了电子进入基层的注入效率。通过在凹槽之间特别设置孔旁路径的宽度，槽的沟槽宽度和布置距离来实现孔的流动控制，从而使载流子的积聚增加基底层，设备的电阻。

8. 发明授权

US5298769A GTO thyristor capable of preventing parasitic thyristors from being generated 失效
标题翻译：能够防止寄生晶闸管产生的GTO晶闸管
公开(公告)号：US5298769A
公开(公告)日：1994-03-29
申请号：US40595
申请日：1993-03-31
申请人： Ichiro Omura , Mitsuhiko Kitagawa
发明人： Ichiro Omura , Mitsuhiko Kitagawa
IPC分类号： H01L29/74 , H01L29/745 , H01L29/749 , H01L27/02 , H01L29/10
CPC分类号： H01L29/7455 , H01L29/7436
摘要： A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET. A thyristor having such a configuration can effectively prevent a latched-up condition caused by parasitic transistors or thyristors to ensure turn off operations of the host thyristor.
摘要翻译： GTO晶闸管包括p型发射极层，n型基极层，p型基极层和n型发射极层。在n型发射极层旁边的p型基极层上形成附加的n型层。附加的p +型层形成在附加的n型层上并且延伸到n型发射极层。阳极电极和阴极电极分别设置在n型发射极层和p型基极层上。 n型发射极层和附加的p +型层通过浮置电极彼此连接。第一栅电极设置在附加p +型层上，附加n型层和p型基极层之间插入有绝缘膜，以形成第一FET。第二栅电极设置在n型基极层上，p型基极层和n型发射极层之间插入绝缘膜，以形成第二FET。具有这种结构的晶闸管可以有效地防止由寄生晶体管或晶闸管引起的锁存状态，以确保主晶闸管的关断操作。

9. 发明授权

US5637909A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5637909A
公开(公告)日：1997-06-10
申请号：US581939
申请日：1996-01-02
申请人： Hiroomi Nakajima , Yasuhiro Katsumata , Hiroshi Iwai , Toshihiko Iinuma , Kazumi Inou , Mitsuhiko Kitagawa , Kouhei Morizuka , Akio Nakagawa , Ichiro Omura
发明人： Hiroomi Nakajima , Yasuhiro Katsumata , Hiroshi Iwai , Toshihiko Iinuma , Kazumi Inou , Mitsuhiko Kitagawa , Kouhei Morizuka , Akio Nakagawa , Ichiro Omura
IPC分类号： H01L21/331 , H01L27/12 , H01L29/73 , H01L29/786 , H01L21/76
CPC分类号： H01L29/66265 , H01L27/1203 , H01L29/66242 , H01L29/7317 , H01L29/78654
摘要： A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.
摘要翻译：在具有氧化硅膜的硅衬底上形成双极晶体管。在氧化硅膜上形成具有（100）面的顶面的n型硅层，作为集电体层使用。使用KOH水溶液通过蚀刻在集电体层的端部上形成由（111）面构成的端面。通过外延生长在端面上形成B掺杂的p硅层，并用作基底层。此外，在基极层上形成As掺杂的n硅层，并用作发射极层。电极分别连接到集电极，基极和发射极层。

10. 发明授权

US5838026A Insulated-gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US5838026A
公开(公告)日：1998-11-17
申请号：US827530
申请日：1997-03-28
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/36
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

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