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1. 发明授权

US08841648B2 Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US08841648B2
公开(公告)日：2014-09-23
申请号：US12904802
申请日：2010-10-14
申请人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24 , G11C13/00 , G11C11/56
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

2. 发明申请

US20120091427A1 MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US20120091427A1
公开(公告)日：2012-04-19
申请号：US12904802
申请日：2010-10-14
申请人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

3. 发明申请

US20100301449A1 METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY 审中-公开
标题翻译：用三维存储器阵列形成直线和立柱结构的方法和装置，使用双重偏移过程和压印平版印刷
公开(公告)号：US20100301449A1
公开(公告)日：2010-12-02
申请号：US12856392
申请日：2010-08-13
申请人： Roy E. Scheuerlein , Yung-Tin Chen
发明人： Roy E. Scheuerlein , Yung-Tin Chen
IPC分类号： H01L27/02 , H01L21/02 , B29C59/02
CPC分类号： H01L27/1021 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L21/76807 , H01L21/76817 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L29/8613 , H01L29/868 , H01L2221/1021
摘要： The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed.
摘要翻译：本发明提供使用多深度压印光刻掩模和双减法处理形成三维存储器阵列的系统，装置和方法。描述了用于制造三维存储器中的存储层的压印光刻掩模。掩模包括形成有用于在双减法中使用的转印材料中进行印记的特征的半透明材料，所述掩模具有多个印痕深度。至少一个压印深度对应于用于形成存储器线的轨道，并且至少一个深度对应于用于形成存储器单元的柱。公开了许多其他方面。

4. 发明授权

US07781269B2 Triangle two dimensional complementary patterning of pillars 有权
标题翻译：支柱三角形二维互补图案化
公开(公告)号：US07781269B2
公开(公告)日：2010-08-24
申请号：US12216109
申请日：2008-06-30
申请人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
发明人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物，用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。每三个相邻的柱形成等边三角形，每个柱包括半导体器件。多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

5. 发明申请

US20120127779A1 Re-writable Resistance-Switching Memory With Balanced Series Stack 有权
标题翻译：具有平衡串联堆叠的可重写电阻切换存储器
公开(公告)号：US20120127779A1
公开(公告)日：2012-05-24
申请号：US13363252
申请日：2012-01-31
申请人： Roy E. Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
发明人： Roy E. Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
IPC分类号： G11C11/00
CPC分类号： H01L45/146 , G11C5/02 , G11C8/08 , G11C8/12 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/33 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.
摘要翻译：可重写电阻切换存储单元包括串联的第一和第二电容器。第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

6. 发明申请

US20090321789A1 Triangle two dimensional complementary patterning of pillars 有权
标题翻译：支柱三角形二维互补图案化
公开(公告)号：US20090321789A1
公开(公告)日：2009-12-31
申请号：US12216109
申请日：2008-06-30
申请人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
发明人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
IPC分类号： H01L21/822 , H01L27/10
CPC分类号： H01L27/101 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物，用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。每三个相邻的柱形成等边三角形，每个柱包括半导体器件。多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

7. 发明授权

US07733685B2 Cross point memory cell with distributed diodes and method of making same 有权
标题翻译：具有分布二极管的交叉点存储单元及其制造方法
公开(公告)号：US07733685B2
公开(公告)日：2010-06-08
申请号：US12216678
申请日：2008-07-09
申请人： Roy E. Scheuerlein , Luca Fasoli
发明人： Roy E. Scheuerlein , Luca Fasoli
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C17/16 , G11C2213/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/35 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/81 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L27/2472
摘要： A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.
摘要翻译：交叉点存储单元包括第一分布二极管的一部分，第二分布二极管的一部分，位于第一分布二极管的部分和第二分布二极管的部分之间的存储层，电连接到第二分布二极管的位线第一分布二极管和与第二分布二极管电连接的字线。

8. 发明申请

US20100008124A1 Cross point memory cell with distributed diodes and method of making same 有权
公开(公告)号：US20100008124A1
公开(公告)日：2010-01-14
申请号：US12216678
申请日：2008-07-09
申请人： Roy E. Scheuerlein , Luca Fasoli
发明人： Roy E. Scheuerlein , Luca Fasoli
IPC分类号： G11C11/34 , G11C11/00 , H01L21/82
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C17/16 , G11C2213/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/35 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/81 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L27/2472
摘要： A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.

9. 发明申请

US20110149631A1 Rewritable Memory Device with Multi-Level, Write-Once Memory Cells 有权
标题翻译：具有多级，一次写入存储单元的可重写存储器件
公开(公告)号：US20110149631A1
公开(公告)日：2011-06-23
申请号：US12643561
申请日：2009-12-21
申请人： Roy E. Scheuerlein , Luca Fasoli
发明人： Roy E. Scheuerlein , Luca Fasoli
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C11/5692 , G11C16/349 , G11C17/16 , G11C2211/5641 , G11C2211/5646
摘要： The embodiments described herein are directed to a memory device with multi-level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device also contains circuitry configured to select a group of memory cells from the memory array, and read a set of flag bits associated with the group of memory cells. The set of flag bits indicate a number of times the group of memory cells has been written to. The circuitry is also configured to select a threshold read level appropriate for the number of times the group of memory cells has been written to, and for each memory cell in the group, read the memory cell as an unprogrammed single-bit memory cell or as a programmed single-bit memory cell based on the selected threshold read level.
摘要翻译：这里描述的实施例涉及具有多级，一次写入存储器单元的存储器件。在一个实施例中，存储器装置具有包括多个多级一次写入存储器单元的存储器阵列，其中每个存储器单元可编程为多个电阻率水平中的一个。存储器件还包含被配置为从存储器阵列中选择一组存储器单元的电路，并且读取与该组存储器单元相关联的一组标志位。该组标志位指示存储器单元组被写入的次数。电路还被配置为选择适合于已经写入存储器单元组的次数的阈值读取电平，并且对于组中的每个存储器单元，读取作为未编程的单位存储器单元的存储器单元或者作为基于所选择的阈值读取电平的编程的单位存储器单元。

10. 发明申请

US20110032774A1 Semiconductor Memory With Improved Memory Block Switching 有权
标题翻译：具有改进的存储器块切换的半导体存储器
公开(公告)号：US20110032774A1
公开(公告)日：2011-02-10
申请号：US12538492
申请日：2009-08-10
申请人： Thomas Yan , Luca Fasoli , Roy E. Scheuerlein
发明人： Thomas Yan , Luca Fasoli , Roy E. Scheuerlein
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译：非易失性存储器核心包括一个或多个存储器空间。每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。在存储器操作期间，存储器块被转换为活动状态和非活动状态。将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一存储块之间的电荷共享成为可能。这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。

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