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1. 发明授权

US07781269B2 Triangle two dimensional complementary patterning of pillars 有权
标题翻译：支柱三角形二维互补图案化
公开(公告)号：US07781269B2
公开(公告)日：2010-08-24
申请号：US12216109
申请日：2008-06-30
申请人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
发明人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物，用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。每三个相邻的柱形成等边三角形，每个柱包括半导体器件。多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

2. 发明申请

US20090321789A1 Triangle two dimensional complementary patterning of pillars 有权
标题翻译：支柱三角形二维互补图案化
公开(公告)号：US20090321789A1
公开(公告)日：2009-12-31
申请号：US12216109
申请日：2008-06-30
申请人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
发明人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
IPC分类号： H01L21/822 , H01L27/10
CPC分类号： H01L27/101 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物，用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。每三个相邻的柱形成等边三角形，每个柱包括半导体器件。多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

3. 发明授权

US08693233B2 Re-writable resistance-switching memory with balanced series stack 有权
标题翻译：具有平衡串联堆叠的可重写电阻切换存储器
公开(公告)号：US08693233B2
公开(公告)日：2014-04-08
申请号：US13363252
申请日：2012-01-31
申请人： Roy E Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
发明人： Roy E Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
IPC分类号： G11C11/00
CPC分类号： H01L45/146 , G11C5/02 , G11C8/08 , G11C8/12 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/33 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.
摘要翻译：可重写电阻切换存储单元包括串联的第一和第二电容器。第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

4. 发明申请

US20100301449A1 METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY 审中-公开
标题翻译：用三维存储器阵列形成直线和立柱结构的方法和装置，使用双重偏移过程和压印平版印刷
公开(公告)号：US20100301449A1
公开(公告)日：2010-12-02
申请号：US12856392
申请日：2010-08-13
申请人： Roy E. Scheuerlein , Yung-Tin Chen
发明人： Roy E. Scheuerlein , Yung-Tin Chen
IPC分类号： H01L27/02 , H01L21/02 , B29C59/02
CPC分类号： H01L27/1021 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L21/76807 , H01L21/76817 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L29/8613 , H01L29/868 , H01L2221/1021
摘要： The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed.
摘要翻译：本发明提供使用多深度压印光刻掩模和双减法处理形成三维存储器阵列的系统，装置和方法。描述了用于制造三维存储器中的存储层的压印光刻掩模。掩模包括形成有用于在双减法中使用的转印材料中进行印记的特征的半透明材料，所述掩模具有多个印痕深度。至少一个压印深度对应于用于形成存储器线的轨道，并且至少一个深度对应于用于形成存储器单元的柱。公开了许多其他方面。

5. 发明授权

US08841648B2 Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US08841648B2
公开(公告)日：2014-09-23
申请号：US12904802
申请日：2010-10-14
申请人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24 , G11C13/00 , G11C11/56
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

6. 发明申请

US20120127779A1 Re-writable Resistance-Switching Memory With Balanced Series Stack 有权
标题翻译：具有平衡串联堆叠的可重写电阻切换存储器
公开(公告)号：US20120127779A1
公开(公告)日：2012-05-24
申请号：US13363252
申请日：2012-01-31
申请人： Roy E. Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
发明人： Roy E. Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
IPC分类号： G11C11/00
CPC分类号： H01L45/146 , G11C5/02 , G11C8/08 , G11C8/12 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/33 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.
摘要翻译：可重写电阻切换存储单元包括串联的第一和第二电容器。第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

7. 发明申请

US20120091427A1 MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US20120091427A1
公开(公告)日：2012-04-19
申请号：US12904802
申请日：2010-10-14
申请人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

8. 发明申请

US20100105210A1 Method of making pillars using photoresist spacer mask 有权
标题翻译：使用光刻胶掩模掩模制作柱的方法
公开(公告)号：US20100105210A1
公开(公告)日：2010-04-29
申请号：US12289396
申请日：2008-10-27
申请人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan
发明人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan
IPC分类号： H01L21/311
CPC分类号： H01L21/0337
摘要： A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask.
摘要翻译：制造器件的方法包括在下层上形成第一硬掩模层，在第一硬掩模层上形成第一特征，在第一特征上形成第一间隔层，蚀刻第一间隔层以形成第一间隔图案，为了暴露第一特征的顶部，去除第一特征，使用第一间隔图案作为掩模来图案化第一硬掩模以形成第一硬掩模特征，去除第一间隔图案。该方法还包括在第一硬掩模特征上形成第二特征，在第二特征上形成第二间隔层，蚀刻第二间隔层以形成第二间隔图案并暴露第二特征的顶部，去除第二特征，蚀刻第一硬掩模使用第二间隔图案作为掩模形成第二硬掩模特征，并且使用第二硬掩模特征作为掩模蚀刻至少部分下层。

9. 发明授权

US08080443B2 Method of making pillars using photoresist spacer mask 有权
标题翻译：使用光刻胶掩模掩模制作柱的方法
公开(公告)号：US08080443B2
公开(公告)日：2011-12-20
申请号：US12289396
申请日：2008-10-27
申请人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan
发明人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan
IPC分类号： H01L21/44
CPC分类号： H01L21/0337
摘要： A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask.
摘要翻译：制造器件的方法包括在下层上形成第一硬掩模层，在第一硬掩模层上形成第一特征，在第一特征上形成第一间隔层，蚀刻第一间隔层以形成第一间隔图案，为了暴露第一特征的顶部，去除第一特征，使用第一间隔图案作为掩模来图案化第一硬掩模以形成第一硬掩模特征，去除第一间隔图案。该方法还包括在第一硬掩模特征上形成第二特征，在第二特征上形成第二间隔层，蚀刻第二间隔层以形成第二间隔图案并暴露第二特征的顶部，去除第二特征，蚀刻第一硬掩模使用第二间隔图案作为掩模形成第二硬掩模特征，并且使用第二硬掩模特征作为掩模蚀刻至少部分下层。

10. 发明授权

US08076056B2 Method of making sub-resolution pillar structures using undercutting technique 有权
标题翻译：使用底切技术制作分辨率柱状结构的方法
公开(公告)号：US08076056B2
公开(公告)日：2011-12-13
申请号：US12285466
申请日：2008-10-06
申请人： Chun-Ming Wang , Steven Maxwell , Paul Wai Kie Poon , Yung-Tin Chen
发明人： Chun-Ming Wang , Steven Maxwell , Paul Wai Kie Poon , Yung-Tin Chen
IPC分类号： G03F7/26
CPC分类号： H01L21/0334 , H01L21/0338
摘要： A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask.
摘要翻译：一种制造器件的方法包括在下面的层上形成下面的掩模层，在下面的掩模层之上形成第一掩模层，对第一掩模层进行图案化以形成第一掩模特征，利用下面的掩模层来切割下面的掩模特征，使用第一掩模作为掩模，去除第一掩模特征，并使用至少底层掩模特征作为掩模来图案化底层。

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