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1. 发明授权

US08050109B2 Semiconductor memory with improved memory block switching 有权
标题翻译：半导体存储器具有改进的存储块切换
公开(公告)号：US08050109B2
公开(公告)日：2011-11-01
申请号：US12538492
申请日：2009-08-10
申请人： Thomas Yan , Luca Fasoli , Roy E Scheuerlein
发明人： Thomas Yan , Luca Fasoli , Roy E Scheuerlein
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译：非易失性存储器核心包括一个或多个存储器空间。每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。在存储器操作期间，存储器块被转换为活动状态和非活动状态。将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一个存储块之间的电荷共享成为可能。这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。

2. 发明申请

US20110032774A1 Semiconductor Memory With Improved Memory Block Switching 有权
标题翻译：具有改进的存储器块切换的半导体存储器
公开(公告)号：US20110032774A1
公开(公告)日：2011-02-10
申请号：US12538492
申请日：2009-08-10
申请人： Thomas Yan , Luca Fasoli , Roy E. Scheuerlein
发明人： Thomas Yan , Luca Fasoli , Roy E. Scheuerlein
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译：非易失性存储器核心包括一个或多个存储器空间。每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。在存储器操作期间，存储器块被转换为活动状态和非活动状态。将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一存储块之间的电荷共享成为可能。这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。

3. 发明申请

US20120002476A1 Semiconductor Memory With Improved Block Switching 有权
标题翻译：半导体存储器改进块切换
公开(公告)号：US20120002476A1
公开(公告)日：2012-01-05
申请号：US13233602
申请日：2011-09-15
申请人： Thomas Yan , Luca Fasoli , Roy E. Scheuerlein
发明人： Thomas Yan , Luca Fasoli , Roy E. Scheuerlein
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译：非易失性存储器核心包括一个或多个存储器空间。每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。在存储器操作期间，存储器块被转换为活动状态和非活动状态。将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一个存储块之间的电荷共享成为可能。这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。

4. 发明授权

US08320196B2 Semiconductor memory with improved block switching 有权
标题翻译：半导体存储器具有改进的块切换
公开(公告)号：US08320196B2
公开(公告)日：2012-11-27
申请号：US13233602
申请日：2011-09-15
申请人： Thomas Yan , Luca Fasoli , Roy E Scheuerlein
发明人： Thomas Yan , Luca Fasoli , Roy E Scheuerlein
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译：非易失性存储器核心包括一个或多个存储器空间。每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。在存储器操作期间，存储器块被转换为活动状态和非活动状态。将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一存储块之间的电荷共享成为可能。这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。

5. 发明授权

US08841648B2 Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US08841648B2
公开(公告)日：2014-09-23
申请号：US12904802
申请日：2010-10-14
申请人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24 , G11C13/00 , G11C11/56
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

6. 发明授权

US07733685B2 Cross point memory cell with distributed diodes and method of making same 有权
标题翻译：具有分布二极管的交叉点存储单元及其制造方法
公开(公告)号：US07733685B2
公开(公告)日：2010-06-08
申请号：US12216678
申请日：2008-07-09
申请人： Roy E. Scheuerlein , Luca Fasoli
发明人： Roy E. Scheuerlein , Luca Fasoli
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C17/16 , G11C2213/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/35 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/81 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L27/2472
摘要： A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.
摘要翻译：交叉点存储单元包括第一分布二极管的一部分，第二分布二极管的一部分，位于第一分布二极管的部分和第二分布二极管的部分之间的存储层，电连接到第二分布二极管的位线第一分布二极管和与第二分布二极管电连接的字线。

7. 发明申请

US20100008124A1 Cross point memory cell with distributed diodes and method of making same 有权
公开(公告)号：US20100008124A1
公开(公告)日：2010-01-14
申请号：US12216678
申请日：2008-07-09
申请人： Roy E. Scheuerlein , Luca Fasoli
发明人： Roy E. Scheuerlein , Luca Fasoli
IPC分类号： G11C11/34 , G11C11/00 , H01L21/82
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C17/16 , G11C2213/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/35 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/81 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L27/2472
摘要： A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.

8. 发明申请

US20110149631A1 Rewritable Memory Device with Multi-Level, Write-Once Memory Cells 有权
标题翻译：具有多级，一次写入存储单元的可重写存储器件
公开(公告)号：US20110149631A1
公开(公告)日：2011-06-23
申请号：US12643561
申请日：2009-12-21
申请人： Roy E. Scheuerlein , Luca Fasoli
发明人： Roy E. Scheuerlein , Luca Fasoli
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C11/5692 , G11C16/349 , G11C17/16 , G11C2211/5641 , G11C2211/5646
摘要： The embodiments described herein are directed to a memory device with multi-level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device also contains circuitry configured to select a group of memory cells from the memory array, and read a set of flag bits associated with the group of memory cells. The set of flag bits indicate a number of times the group of memory cells has been written to. The circuitry is also configured to select a threshold read level appropriate for the number of times the group of memory cells has been written to, and for each memory cell in the group, read the memory cell as an unprogrammed single-bit memory cell or as a programmed single-bit memory cell based on the selected threshold read level.
摘要翻译：这里描述的实施例涉及具有多级，一次写入存储器单元的存储器件。在一个实施例中，存储器装置具有包括多个多级一次写入存储器单元的存储器阵列，其中每个存储器单元可编程为多个电阻率水平中的一个。存储器件还包含被配置为从存储器阵列中选择一组存储器单元的电路，并且读取与该组存储器单元相关联的一组标志位。该组标志位指示存储器单元组被写入的次数。电路还被配置为选择适合于已经写入存储器单元组的次数的阈值读取电平，并且对于组中的每个存储器单元，读取作为未编程的单位存储器单元的存储器单元或者作为基于所选择的阈值读取电平的编程的单位存储器单元。

9. 发明申请

US20100271885A1 Reduced complexity array line drivers for 3D matrix arrays 有权
标题翻译：降低3D矩阵阵列的复杂性阵列线驱动
公开(公告)号：US20100271885A1
公开(公告)日：2010-10-28
申请号：US12385964
申请日：2009-04-24
申请人： Roy E. Scheuerlein , Luca Fasoli
发明人： Roy E. Scheuerlein , Luca Fasoli
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C11/22 , G11C5/025 , G11C5/063 , G11C8/10 , G11C8/12 , G11C11/16 , G11C13/0002 , G11C13/0026 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or second plurality of Y lines and one of the plurality of X lines, respectively. Substantially all of the first plurality and second plurality of Y lines are driven to a Y line unselect voltage. At least one selected Y line of the first plurality of Y lines is driven to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage.
摘要翻译：一种偏置非易失性存储器阵列的方法。非易失性存储器阵列包括第一和第二多个Y线，多个X线，第一和第二多个两个终端存储器单元。每个第一和第二存储器单元分别耦合到第一或第二多个Y线中的一个和多个X线中的一个。基本上所有的第一和第二多个Y线被驱动到Y线取消选择电压。将第一多个Y线中的至少一个所选择的Y线驱动到Y线选择电压，同时浮置第一多条Y线的剩余Y线，同时将基本上所有的第二多条Y线驱动到Y线取消选择电压。

10. 发明授权

US07177183B2 Multiple twin cell non-volatile memory array and logic block structure and method therefor 有权
标题翻译：多个单元非易失性存储器阵列及其逻辑块结构及其方法
公开(公告)号：US07177183B2
公开(公告)日：2007-02-13
申请号：US10675212
申请日：2003-09-30
申请人： Roy E. Scheuerlein , Luca Fasoli , Mark G. Johnson
发明人： Roy E. Scheuerlein , Luca Fasoli , Mark G. Johnson
IPC分类号： G11C16/04
CPC分类号： G11C15/046 , G11C8/10 , G11C8/14 , G11C16/10 , G11C16/16
摘要： Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.
摘要翻译：非常密集的存储单元结构提供了用于实现内存和逻辑功能的新数组结构。示例性非易失性存储器阵列包括被配置为在读取操作模式下在逻辑上相同的第一多个X线，并且每个X线与与至少一个Y线编号的第一Y线组相关联。第一多个X线中的每一个也可以与编号至少一个Y线的第二Y线组相关联。在一些实施例中，第一和第二Y线组可以以读取模式同时选择，并且当这样选择时，它们分别耦合到读出放大器电路的真实和补码输入。这样的Y线组可以仅编号一条Y线，或者可以编号多于一条Y线。可以在2D或3D存储器阵列中使用许多类型的存储单元，例如各种无源元件单元和EEPROM单元。这样的阵列可以被配置为存储数据，或被配置为执行阈值逻辑或被配置为内容可寻址存储器阵列的存储器。

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