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1. 发明申请

US20050084990A1 Endpoint detection in manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件中的端点检测
公开(公告)号：US20050084990A1
公开(公告)日：2005-04-21
申请号：US10685484
申请日：2003-10-16
申请人： Yuh-Turng Liu , Kuang-Chao Chen , Hsueh-Hao Shih , Yun-Chi Yang , Yung-Tai Hung
发明人： Yuh-Turng Liu , Kuang-Chao Chen , Hsueh-Hao Shih , Yun-Chi Yang , Yung-Tai Hung
IPC分类号： G01R31/26 , H01L21/302 , H01L21/3105 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/66 , H01L21/768
CPC分类号： H01L21/31053 , H01L21/76819
摘要： A method of manufacturing a semiconductor device that comprises the steps of providing a semiconductor wafer including a patterned layer, forming a first insulating layer over the patterned layer of the semiconductor wafer, the first insulating layer including a first index of refraction, forming a second insulating layer over the first insulating layer, the second insulating layer including a second index of refraction smaller than the first index of refraction, removing the second insulating layer by a planarizing process, and detecting a change in index of refraction during the planarizing process.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：提供包括图案化层的半导体晶片，在半导体晶片的图案化层上形成第一绝缘层，第一绝缘层包括第一折射率，形成第二绝缘层第二绝缘层包括小于第一折射率的第二折射率，通过平坦化处理去除第二绝缘层，并且在平坦化处理期间检测折射率的变化。

2. 发明授权

US06824452B1 Polishing pad and process of chemical mechanical use thereof 有权
标题翻译：抛光垫及其化学机械使用过程
公开(公告)号：US06824452B1
公开(公告)日：2004-11-30
申请号：US10605425
申请日：2003-09-30
申请人： Yung-Tai Hung , Yuhturng Liu , Hsueh-Hao Shih , Kuang-Chao Chen
发明人： Yung-Tai Hung , Yuhturng Liu , Hsueh-Hao Shih , Kuang-Chao Chen
IPC分类号： B24B100
CPC分类号： B24B37/24 , B24B37/042 , B24D3/32 , B24D13/147
摘要： A chemical mechanical polishing to polish a substrate having a layer to be polished thereon is described. A pre-polishing process is performed using a softer polishing pad to remove partially raised parts of the layer to be polished before conducting a polishing process using a harder polishing pad. Since the first polishing pad is flexible, porous and with low density, the first polishing pad can be deformed to increase contact areas between the first polishing pad and the raised part of the layer to be polished, and the abrasives are embedded easily in holes of the surface of the first polishing pad. Ultimately, the layer to be polished can be polished directly during the pre-polishing process. Therefore, the processing time is reduced, the consumption of the slurry is decreased and the process cost can be cut down substantially.
摘要翻译：描述了对具有待抛光层的基板进行化学机械抛光。在使用更硬的抛光垫进行抛光处理之前，使用较软的抛光垫进行预抛光工艺以去除待抛光层的部分凸起部分。由于第一抛光垫是柔性的，多孔的并且具有低密度，所以第一抛光垫可以变形以增加第一抛光垫与被抛光层的凸起部分之间的接触面积，并且磨料易于嵌入到第一抛光垫的表面。最终，抛光过程中可以直接抛光抛光层。因此，处理时间缩短，浆料的消耗量减少，工序成本大幅降低。

3. 发明申请

US20050009337A1 [METAL SILICIDE STRUCTURE AND METHOD OF FORMING THE SAME] 审中-公开
标题翻译： [金属硅化物结构及其形成方法]
公开(公告)号：US20050009337A1
公开(公告)日：2005-01-13
申请号：US10604835
申请日：2003-08-21
申请人： Hung-Wei Liu , Kuang-Chao Chen , Hsueh-Hao Shih
发明人： Hung-Wei Liu , Kuang-Chao Chen , Hsueh-Hao Shih
IPC分类号： H01L21/265 , H01L21/285 , H01L21/44
CPC分类号： H01L21/28518
摘要： A method of forming a suicide layer is described. A silicon layer is provided. Ions are introduced in the silicon layer. A metal layer is formed on the silicon layer. An annealing process is performed so that the silicon layer reacts with the metal layer to form the metal silicide layer. Thereafter, the unreacted metal layer is removed. The uniformity of the grain size and the grain distribution of the metal silicide layer are improved by introducing the ions in the silicon layer before performing the annealing process, so that sheet resistance of the metal silicide layer is reduced.
摘要翻译：描述了形成硅化物层的方法。提供硅层。硅在硅层中引入了离子。在硅层上形成金属层。执行退火处理，使得硅层与金属层反应以形成金属硅化物层。之后，除去未反应的金属层。在进行退火处理之前，通过在硅层中引入离子来改善金属硅化物层的晶粒尺寸和晶粒分布的均匀性，从而降低金属硅化物层的薄层电阻。

4. 发明授权

US06887757B2 Method of manufacturing flash memory 有权
标题翻译：闪存制造方法
公开(公告)号：US06887757B2
公开(公告)日：2005-05-03
申请号：US10249867
申请日：2003-05-14
申请人： Kuang-Chao Chen , Hsueh-Hao Shih , Ling-Wuu Yang
发明人： Kuang-Chao Chen , Hsueh-Hao Shih , Ling-Wuu Yang
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a flash memory device is provided. First, a substrate partitioned into a memory cell region and a peripheral circuit region is provided. A tunnel dielectric layer is formed over the memory cell region and a liner layer is formed over the peripheral circuit region. Thereafter, a patterned gate conductive layer is formed over the substrate. An inter-gate dielectric layer and a passivation layer are sequentially formed over the substrate. The passivation layer, the inter-gate dielectric layer, the gate conductive layer and the liner layer over the peripheral circuit region are removed. A gate dielectric layer is formed over the peripheral circuit region while the passivation layer over the memory cell region is converted into an oxide layer. Another conductive layer is formed over the substrate. The conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region are patterned to form a memory gate. The second conductive layer over the peripheral circuit region is similarly patterned to form a gate.
摘要翻译：提供一种制造闪速存储器件的方法。首先，提供分割为存储单元区域和外围电路区域的基板。在存储单元区域上形成隧道介电层，并在外围电路区域上形成衬垫层。此后，在衬底上形成图案化的栅极导电层。栅极间电介质层和钝化层依次形成在衬底上。外围电路区域上的钝化层，栅极间电介质层，栅极导电层和衬垫层被去除。在外围电路区域上形成栅极电介质层，同时将存储单元区域上的钝化层转换成氧化物层。在衬底上形成另一导电层。将存储单元区域上的导电层，氧化物层，栅极间电介质层和栅极导电层图案化以形成存储栅极。外围电路区域上的第二导电层类似地构图形成栅极。

5. 发明授权

US06677255B1 Method for removing fences without reduction of ONO film thickness 有权
标题翻译：除去ONO膜厚度的方法
公开(公告)号：US06677255B1
公开(公告)日：2004-01-13
申请号：US10230328
申请日：2002-08-29
申请人： Hsueh-Hao Shih , Kuang-Chao Chen
发明人： Hsueh-Hao Shih , Kuang-Chao Chen
IPC分类号： H01L2131
CPC分类号： H01L29/6653 , H01L21/28273 , H01L21/31116 , H01L21/31144 , H01L29/66825 , Y10S438/954
摘要： A method of manufacturing a semiconductor device including providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over the layer of stacked oxide-nitride-oxide layer, providing a layer of photoresist over the first silicon layer, patterning and defining the photoresist layer, etching the first silicon layer and stacked oxide-nitride-oxide layer unmasked by the photoresist, removing the photoresist layer, providing a cleaning solution to the stacked oxide-nitride-oxide layer with the first silicon layer as a mask, and depositing a second layer of polysilicon over the first silicon layer to form a combined silicon layer.
摘要翻译：一种制造半导体器件的方法，包括提供第一层，在第一层上形成层叠的氧化物 - 氮化物 - 氧化物层的层，在层叠的氧化物 - 氮化物 - 氧化物层的层上沉积第一硅层，提供层在第一硅层上的光致抗蚀剂，图案化和限定光致抗蚀剂层，蚀刻由光致抗蚀剂未被掩模的第一硅层和层叠的氧化物 - 氮化物 - 氧化物层，去除光致抗蚀剂层，为层叠的氧化物 - 氮化物 - 氧化物层提供清洁溶液以第一硅层作为掩模，并在第一硅层上沉积第二层多晶硅以形成组合的硅层。

6. 发明授权

US06911374B2 Fabrication method for shallow trench isolation region 有权
标题翻译：浅沟槽隔离区的制作方法
公开(公告)号：US06911374B2
公开(公告)日：2005-06-28
申请号：US10604615
申请日：2003-08-05
申请人： Chin Hsiang Lin , Chin-Wei Liao , Hsueh-Hao Shih , Kuang-Chao Chen
发明人： Chin Hsiang Lin , Chin-Wei Liao , Hsueh-Hao Shih , Kuang-Chao Chen
IPC分类号： H01L21/762 , H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76232 , H01L21/31111 , H01L21/31155
摘要： A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation layer. The surface treated layer is then removed, followed by forming a second insulation layer on the first insulation layer and filling the trench to form a shallow trench isolation region. Since a part of the trench is first filled with the first insulation layer, followed by removing a portion of the first insulation layer, the aspect ratio of the trench is lower before the filling of the second insulation in the trench. The adverse result, such as, void formation in the shallow trench isolation region due to a high aspect ratio, is thus prevented.
摘要翻译：描述了浅沟槽隔离区域的制造方法。沟槽的一部分填充有第一绝缘层，随后进行表面处理工艺以在第一绝缘层的一部分的表面上形成表面处理层。然后去除表面处理层，随后在第一绝缘层上形成第二绝缘层，并填充沟槽以形成浅沟槽隔离区域。由于沟槽的一部分首先填充有第一绝缘层，接着除去第一绝缘层的一部分，沟槽的纵横比在填充沟槽中的第二绝缘体之前较低。因此防止由于高纵横比而导致浅沟槽隔离区域中的空隙形成的不良结果。

7. 发明授权

US08047899B2 Pad and method for chemical mechanical polishing 有权
标题翻译：化学机械抛光垫和方法
公开(公告)号：US08047899B2
公开(公告)日：2011-11-01
申请号：US11878654
申请日：2007-07-26
申请人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
发明人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
IPC分类号： B24B7/22 , B24D3/34
CPC分类号： B24B37/24 , B24D3/346
摘要： A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.
摘要翻译：提供了半导体器件的两个相邻结构的化学机械抛光方法。一种用于机械抛光的方法，包括：（a）提供半导体器件，其包括在其表面形成的凹部，形成在所述表面上的第一层，以及填充有所述凹部并形成在所述第一层上的第二层; 和（b）用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层，其中该垫包括第二层的腐蚀抑制剂。

8. 发明申请

US20090029551A1 Pad and method for chemical mechanical polishing 有权
标题翻译：化学机械抛光垫和方法
公开(公告)号：US20090029551A1
公开(公告)日：2009-01-29
申请号：US11878654
申请日：2007-07-26
申请人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
发明人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
IPC分类号： H01L21/461 , C09K13/00
CPC分类号： B24B37/24 , B24D3/346
摘要： A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.
摘要翻译：提供了半导体器件的两个相邻结构的化学机械抛光方法。一种用于机械抛光的方法，包括：（a）提供半导体器件，其包括在其表面形成的凹部，形成在所述表面上的第一层，以及填充有所述凹部并形成在所述第一层上的第二层; 和（b）用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层，其中该垫包括第二层的腐蚀抑制剂。

9. 发明申请

US20120040532A1 PAD AND METHOD FOR CHEMICAL MECHANICAL POLISHING 审中-公开
标题翻译： PAD和化学机械抛光方法
公开(公告)号：US20120040532A1
公开(公告)日：2012-02-16
申请号：US13281162
申请日：2011-10-25
申请人： Chun-Fu CHEN , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
发明人： Chun-Fu CHEN , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
IPC分类号： H01L21/306
CPC分类号： B24B37/24 , B24D3/346
摘要： A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.
摘要翻译：提供了半导体器件的两个相邻结构的化学机械抛光方法。一种用于机械抛光的方法，包括：（a）提供半导体器件，其包括在其表面形成的凹部，形成在所述表面上的第一层，以及填充有所述凹部并形成在所述第一层上的第二层; 和（b）用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层，其中该垫包括第二层的腐蚀抑制剂。

10. 发明申请

US20050037578A1 [METHOD FOR FORMING AN OXIDE/ NITRIDE/OXIDE STACKED LAYER] 审中-公开
标题翻译： [形成氧化物/氮化物/氧化物堆叠层的方法]
公开(公告)号：US20050037578A1
公开(公告)日：2005-02-17
申请号：US10604764
申请日：2003-08-14
申请人： Wei Wen Chen , Tzung-Ting Han , Yun-Chi Yang , Ling-Wuu Yang , Kuang-Chao Chen
发明人： Wei Wen Chen , Tzung-Ting Han , Yun-Chi Yang , Ling-Wuu Yang , Kuang-Chao Chen
IPC分类号： H01L21/28 , H01L21/314 , H01L21/336 , H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/0217 , H01L21/022 , H01L21/02332 , H01L21/3144 , H01L29/40114
摘要： A method for fabricating a silicon oxide/silicon nitride/silicon oxide stacked layer structure is described. A bottom oxide layer is formed over a substrate. A surface treatment is then performed on the first silicon oxide layer to form an interface layer over the bottom oxide layer. The surface treatment is conducted in a nitrogen ambient. Thereafter, a silicon nitride layer is formed over the interface layer, followed by forming an upper silicon oxide layer over the silicon nitride layer.
摘要翻译：描述了制造氧化硅/氮化硅/氧化硅堆叠层结构的方法。在衬底上形成底部氧化物层。然后对第一氧化硅层进行表面处理，以在底部氧化物层上形成界面层。表面处理在氮气环境中进行。此后，在界面层上形成氮化硅层，随后在氮化硅层上形成上部氧化硅层。

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