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1. 发明授权

US08580680B2 Metal silicide formation 有权
标题翻译：金属硅化物形成
公开(公告)号：US08580680B2
公开(公告)日：2013-11-12
申请号：US12915917
申请日：2010-10-29
申请人： Tuung Luoh , Sheng Hui Hsieh , Ricky Huang , Chin-Ta Su , Tahone Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Sheng Hui Hsieh , Ricky Huang , Chin-Ta Su , Tahone Yang , Kuang-Chao Chen
IPC分类号： H01L21/44
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518
摘要： Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, the metal layer comprising metal capable of reacting with external silicon-based portions of the features to form a metal silicide. In addition, such a method may also include depositing a cap layer on the metal layer deposited on and between the plurality of raised silicon-based features, wherein a thickness of the cap layer on the metal layer between the raised features is greater than or equal to a thickness of the cap layer on the metal layer on the raised features. Furthermore, such a method may also include annealing the structure to cause portions of the metal layer to react with portions of the external silicon-based portions of the features to form metal silicide pads on and between the raised features.
摘要翻译：公开了在半导体器件上形成金属硅化物接触焊盘的技术，并且在一个示例性实施例中，一种方法可以包括在形成在半导体衬底上的多个凸起的硅基特征之间和之间沉积金属层，所述金属层包括金属与特征的外部硅基部分反应以形成金属硅化物。此外，这种方法还可以包括在沉积在多个凸起的硅基特征之间和之间的金属层上沉积覆盖层，其中在凸起特征之间的金属层上的覆盖层的厚度大于或等于到金属层上的盖层的厚度在凸起的特征上。此外，这种方法还可以包括对结构进行退火以使金属层的一部分与特征的外部硅基部分的部分反应，以在凸起特征之间和之间形成金属硅化物焊盘。

2. 发明申请

US20120190198A1 METHOD FOR IMPROVING FLATNESS OF A LAYER DEPOSITED ON POLYCRYSTALLINE LAYER 有权
标题翻译：改善沉积在多晶层上的层的平滑度的方法
公开(公告)号：US20120190198A1
公开(公告)日：2012-07-26
申请号：US13012506
申请日：2011-01-24
申请人： Tuung Luoh , Ling-Wu Yang , Ta-Hone Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ling-Wu Yang , Ta-Hone Yang , Kuang-Chao Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/02068 , H01L21/0217 , H01L21/32055 , H01L21/32139 , H01L21/76834
摘要： Described is a method for improving the flatness of a layer deposited on a doped polycrystalline layer, which includes reducing the grain size of the polycrystalline layer to decrease the out-diffusion amount of the dopant from the polycrystalline layer, and/or reducing the amount of the out-diffusing dopant on the surface of the polycrystalline layer.
摘要翻译：描述了一种用于提高沉积在掺杂多晶层上的层的平坦度的方法，其包括减小多晶层的晶粒尺寸以减少掺杂剂从多晶层的扩散量，和/或减少多晶层表面上的扩散扩散掺杂剂。

3. 发明申请

US20120104516A1 METAL SILICIDE FORMATION 有权
标题翻译：金属硅化物形成
公开(公告)号：US20120104516A1
公开(公告)日：2012-05-03
申请号：US12915917
申请日：2010-10-29
申请人： Tuung Luoh , Sheng Hui Hsieh , Ricky Huang , Chin-Ta Su , Tahone Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Sheng Hui Hsieh , Ricky Huang , Chin-Ta Su , Tahone Yang , Kuang-Chao Chen
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518
摘要： Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, the metal layer comprising metal capable of reacting with external silicon-based portions of the features to form a metal silicide. In addition, such a method may also include depositing a cap layer on the metal layer deposited on and between the plurality of raised silicon-based features, wherein a thickness of the cap layer on the metal layer between the raised features is greater than or equal to a thickness of the cap layer on the metal layer on the raised features. Furthermore, such a method may also include annealing the structure to cause portions of the metal layer to react with portions of the external silicon-based portions of the features to form metal silicide pads on and between the raised features.
摘要翻译：公开了在半导体器件上形成金属硅化物接触焊盘的技术，并且在一个示例性实施例中，一种方法可以包括在形成在半导体衬底上的多个凸起的硅基特征之间和之间沉积金属层，所述金属层包括金属与特征的外部硅基部分反应以形成金属硅化物。此外，这种方法还可以包括在沉积在多个凸起的硅基特征之间和之间的金属层上沉积覆盖层，其中在凸起特征之间的金属层上的覆盖层的厚度大于或等于到金属层上的盖层的厚度在凸起的特征上。此外，这种方法还可以包括对结构进行退火以使金属层的一部分与特征的外部硅基部分的部分反应，以在凸起特征之间和之间形成金属硅化物焊盘。

4. 发明申请

US20120000423A1 HDP-CVD SYSTEM 审中-公开
标题翻译： HDP-CVD系统
公开(公告)号：US20120000423A1
公开(公告)日：2012-01-05
申请号：US13229347
申请日：2011-09-09
申请人： Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen , Shing-Ann Luo
发明人： Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen , Shing-Ann Luo
IPC分类号： C23C16/50
CPC分类号： H01L21/31608 , C23C16/0209 , C23C16/045 , C23C16/401 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/76224
摘要： An HDP-CVD system is described, including an HDP-CVD chamber for depositing a material on a wafer, and a pre-heating chamber disposed outside of the HDP-CVD chamber to pre-heat the wafer, before the wafer is loaded in the HDP-CVD chamber, to a temperature higher than room temperature and required in the deposition step to be conducted in the HDP-CVD chamber. The pre-heating chamber is equipped with a heating lamp for the pre-heating. The wafer has been formed with a trench before being pre-heated.
摘要翻译：描述了一种HDP-CVD系统，其包括用于在晶片上沉积材料的HDP-CVD室和设置在HDP-CVD室外部的预热室，以在晶片装载到晶片之前预热晶片 HDP-CVD室至高于室温的温度，并且在沉积步骤中需要在HDP-CVD室中进行。预热室配备有用于预热的加热灯。在预加热之前，晶片已经形成有沟槽。

5. 发明授权

US08067292B2 Isolation structure, non-volatile memory having the same, and method of fabricating the same 有权
标题翻译：隔离结构，具有相同的非易失性存储器及其制造方法
公开(公告)号：US08067292B2
公开(公告)日：2011-11-29
申请号：US12343633
申请日：2008-12-24
申请人： Ming-Da Cheng , Chin-Tsan Yeh , Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Ming-Da Cheng , Chin-Tsan Yeh , Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/76205
摘要： A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.
摘要翻译：一种形成隔离结构的方法，包括：（a）提供具有凹部的基部; （b）在基座和凹槽中形成停止层; （c）在所述阻挡层上形成电介质材料，以允许所述凹部的其余部分填充所述电介质材料; （d）通过进行化学机械抛光（CMP）工艺在基底上去除电介质材料，直到一部分停止层被暴露以在凹槽中形成电介质层; 和（e）去除所述阻挡层的一部分，其中所述阻挡层的另一部分和填充在所述凹部中的所述电介质层构成所述隔离结构。

6. 发明申请

US20110104881A1 METHOD OF REDUCING WORDLINE SHORTING 有权
标题翻译：减少WORDLINE SHORTING的方法
公开(公告)号：US20110104881A1
公开(公告)日：2011-05-05
申请号：US12611614
申请日：2009-11-03
申请人： Hong-Ji Lee , Nan-Tsu Lian , Kuang-Chao Chen
发明人： Hong-Ji Lee , Nan-Tsu Lian , Kuang-Chao Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/28247 , H01L21/28282 , H01L27/11568
摘要： A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.
摘要翻译：一种制造存储器件的方法包括提供具有绝缘层的衬底，在绝缘层上形成第一，第二和第三导电层，在第三导电层上形成掩模，蚀刻通过第三导电层和第一部分厚度使用所述掩模提供所述第三导电层的蚀刻侧壁部分和所述第二多晶硅层的蚀刻的上表面，以及沿着蚀刻的侧壁部分和所蚀刻的上表面形成衬垫层。

7. 发明申请

US20100038786A1 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20100038786A1
公开(公告)日：2010-02-18
申请号：US12228764
申请日：2008-08-14
申请人： Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/2855 , H01L21/28518 , H01L21/28556 , H01L21/76843 , H01L21/76846 , H01L21/76864
摘要： A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer.
摘要翻译：公开了一种制造半导体器件的方法。提供诸如裸硅的半导体衬底，并且在半导体衬底上形成电介质层。通过去除介电层的一部分，在电介质层内提供开口。在电介质层和开口上形成共形的第一导电层。在第一导电层上形成共形的第二导电层。在第二导电层上形成共形势垒层。

8. 发明申请

US20090184343A1 ISOLATION STRUCTURE, NON-VOLATILE MEMORY HAVING THE SAME, AND METHOD OF FABRICATING THE SAME 有权
标题翻译：隔离结构，具有该隔离结构的非易失性存储器及其制造方法
公开(公告)号：US20090184343A1
公开(公告)日：2009-07-23
申请号：US12343633
申请日：2008-12-24
申请人： Ming-Da Cheng , Chin-Tsan Yeh , Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Ming-Da Cheng , Chin-Tsan Yeh , Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L21/3205
CPC分类号： H01L21/76229 , H01L21/76205
摘要： A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.
摘要翻译：一种形成隔离结构的方法，包括：（a）提供具有凹部的基部; （b）在基座和凹槽中形成停止层; （c）在所述阻挡层上形成电介质材料，以允许所述凹部的其余部分填充所述电介质材料; （d）通过进行化学机械抛光（CMP）工艺在基底上去除电介质材料，直到一部分停止层被暴露以在凹槽中形成电介质层; 和（e）去除所述阻挡层的一部分，其中所述阻挡层的另一部分和填充在所述凹部中的所述电介质层构成所述隔离结构。

9. 发明申请

US20090114973A1 METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS SIMULTANEOUSLY 有权
标题翻译：同时形成自对准联系人和本地互连的方法
公开(公告)号：US20090114973A1
公开(公告)日：2009-05-07
申请号：US12113855
申请日：2008-05-01
申请人： Tuung Luoh , Ling-Wuu Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ling-Wuu Yang , Kuang-Chao Chen
IPC分类号： H01L29/788 , H01L23/52
CPC分类号： H01L27/11521 , H01L21/76895 , H01L21/76897 , H01L27/115
摘要： The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.
摘要翻译：本发明一般涉及半导体，更具体地涉及半导体存储器件结构和改进的制造方法。改进的制造工艺允许自对准触点和局部互连同时处理。该过程允许自对准触点和局部互连之间的最小距离要求加宽，这使得自对准触点和局部互连的图案化变得更容易。扩大的最小距离要求也允许进一步的记忆体细胞收缩。自对准触点和局部互连的改进结构也具有优异的隔离特性。

10. 发明申请

US20090081859A1 Metallization process 审中-公开
标题翻译：金属化过程
公开(公告)号：US20090081859A1
公开(公告)日：2009-03-26
申请号：US11902228
申请日：2007-09-20
申请人： Tuung Luoh , Ling-Wuu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ling-Wuu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28518 , H01L29/665 , H01L29/7833
摘要： A metallization process is provided. The metallization process comprises the following steps. First, a semiconductor base having at least a silicon-containing conductive region is provided. Afterwards, nitrogen ions are implanted into the silicon-containing conductive region. Next, a first thermal process is performed on the semiconductor base for repairing the surface of the semiconductor base. Then, a metal layer is formed on the surface of the semiconductor base and the metal layer covers the silicon-containing conductive region. Lastly, a second thermal process is performed on the semiconductor base covered with the metal layer so as to form a metal silicide layer on the silicon-containing conductive region.
摘要翻译：提供金属化工艺。金属化处理包括以下步骤。首先，提供至少具有含硅导电区域的半导体基底。之后，将氮离子注入含硅导电区域。接下来，对半导体基板进行第一热处理，以修复半导体基底的表面。然后，在半导体基底的表面上形成金属层，并且金属层覆盖含硅导电区域。最后，在覆盖有金属层的半导体基底上进行第二热处理，以在含硅导电区域上形成金属硅化物层。

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