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1. 发明申请

US20050084990A1 Endpoint detection in manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件中的端点检测
公开(公告)号：US20050084990A1
公开(公告)日：2005-04-21
申请号：US10685484
申请日：2003-10-16
申请人： Yuh-Turng Liu , Kuang-Chao Chen , Hsueh-Hao Shih , Yun-Chi Yang , Yung-Tai Hung
发明人： Yuh-Turng Liu , Kuang-Chao Chen , Hsueh-Hao Shih , Yun-Chi Yang , Yung-Tai Hung
IPC分类号： G01R31/26 , H01L21/302 , H01L21/3105 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/66 , H01L21/768
CPC分类号： H01L21/31053 , H01L21/76819
摘要： A method of manufacturing a semiconductor device that comprises the steps of providing a semiconductor wafer including a patterned layer, forming a first insulating layer over the patterned layer of the semiconductor wafer, the first insulating layer including a first index of refraction, forming a second insulating layer over the first insulating layer, the second insulating layer including a second index of refraction smaller than the first index of refraction, removing the second insulating layer by a planarizing process, and detecting a change in index of refraction during the planarizing process.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：提供包括图案化层的半导体晶片，在半导体晶片的图案化层上形成第一绝缘层，第一绝缘层包括第一折射率，形成第二绝缘层第二绝缘层包括小于第一折射率的第二折射率，通过平坦化处理去除第二绝缘层，并且在平坦化处理期间检测折射率的变化。

2. 发明授权

US06677255B1 Method for removing fences without reduction of ONO film thickness 有权
标题翻译：除去ONO膜厚度的方法
公开(公告)号：US06677255B1
公开(公告)日：2004-01-13
申请号：US10230328
申请日：2002-08-29
申请人： Hsueh-Hao Shih , Kuang-Chao Chen
发明人： Hsueh-Hao Shih , Kuang-Chao Chen
IPC分类号： H01L2131
CPC分类号： H01L29/6653 , H01L21/28273 , H01L21/31116 , H01L21/31144 , H01L29/66825 , Y10S438/954
摘要： A method of manufacturing a semiconductor device including providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over the layer of stacked oxide-nitride-oxide layer, providing a layer of photoresist over the first silicon layer, patterning and defining the photoresist layer, etching the first silicon layer and stacked oxide-nitride-oxide layer unmasked by the photoresist, removing the photoresist layer, providing a cleaning solution to the stacked oxide-nitride-oxide layer with the first silicon layer as a mask, and depositing a second layer of polysilicon over the first silicon layer to form a combined silicon layer.
摘要翻译：一种制造半导体器件的方法，包括提供第一层，在第一层上形成层叠的氧化物 - 氮化物 - 氧化物层的层，在层叠的氧化物 - 氮化物 - 氧化物层的层上沉积第一硅层，提供层在第一硅层上的光致抗蚀剂，图案化和限定光致抗蚀剂层，蚀刻由光致抗蚀剂未被掩模的第一硅层和层叠的氧化物 - 氮化物 - 氧化物层，去除光致抗蚀剂层，为层叠的氧化物 - 氮化物 - 氧化物层提供清洁溶液以第一硅层作为掩模，并在第一硅层上沉积第二层多晶硅以形成组合的硅层。

3. 发明授权

US06221744B1 Method for forming a gate 失效
标题翻译：栅极形成方法
公开(公告)号：US06221744B1
公开(公告)日：2001-04-24
申请号：US09234618
申请日：1999-01-20
申请人： Hsueh-Hao Shih , Juan-Yuan Wu , Tri-Rung Yew
发明人： Hsueh-Hao Shih , Juan-Yuan Wu , Tri-Rung Yew
IPC分类号： H02L21305
CPC分类号： H01L21/28035 , H01L29/4925
摘要： A method for forming a gate on a substrate for manufacturing semiconductor devices is described. The present method comprises the step of providing a gate oxide layer on top of a substrate. A polysilicon layer is overlaid on the gate oxide layer and then, a amorphous silicon layer is formed thereon. The stack of amorphous and polysilicon layers is defined to form a gate structure on gate oxide layer. Next, a thermal treatment is performed on the gate structure.
摘要翻译：描述了一种用于在用于制造半导体器件的衬底上形成栅极的方法。本方法包括在衬底的顶部上提供栅氧化层的步骤。在栅氧化层上重叠多晶硅层，然后在其上形成非晶硅层。限定非晶和多晶硅层的堆叠以在栅极氧化物层上形成栅极结构。接下来，对栅极结构进行热处理。

4. 发明授权

US06180492B2 Method of forming a liner for shallow trench isolation 有权
标题翻译：浅沟槽隔离衬垫的形成方法
公开(公告)号：US06180492B2
公开(公告)日：2001-01-30
申请号：US09237298
申请日：1999-01-25
申请人： Hsueh-Hao Shih , Tri-Rung Yew , Water Lur , Gwo-Shii Yang
发明人： Hsueh-Hao Shih , Tri-Rung Yew , Water Lur , Gwo-Shii Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： An improved method for forming shallow trench isolation structure is described. The present method comprises the steps of providing a pad oxide layer and a mask layer on a semiconductor substrate and forming a trench structure therein. Next, a liner oxide layer is formed on the surface of the trench structure in the semiconductor substrate and is extensively formed on the side surface of the mask layer exposed therein and the top surface of the mask layer by wet oxidation. A dielectric material is deposited on the liner oxide layer and fills the trench structure. The dielectric material layer is planarized. The mask layer and the pad oxide layer are then removed to form the isolation structures. The method for forming the shallow trench structures on a semiconductor structure in accordance with the present invention can eliminate the kink effect that occurs in the conventional method.
摘要翻译：描述了一种用于形成浅沟槽隔离结构的改进方法。本方法包括以下步骤：在半导体衬底上提供衬垫氧化物层和掩模层，并在其中形成沟槽结构。接下来，在半导体衬底中的沟槽结构的表面上形成衬垫氧化物层，并且通过湿氧化在其中暴露于其中的掩模层的侧表面和掩模层的顶表面上广泛地形成衬里氧化物层。电介质材料沉积在衬垫氧化物层上并填充沟槽结构。介电材料层被平坦化。然后去除掩模层和焊盘氧化物层以形成隔离结构。根据本发明的在半导体结构上形成浅沟槽结构的方法可以消除在常规方法中发生的扭结效应。

5. 发明授权

US6001694A Manufacturing method for integrated circuit dielectric layer 失效
标题翻译：集成电路介质层的制造方法
公开(公告)号：US6001694A
公开(公告)日：1999-12-14
申请号：US059752
申请日：1998-04-14
申请人： Hsueh-Hao Shih , Juan-Yuan Wu , Water Lur
发明人： Hsueh-Hao Shih , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21/28 , H01L29/51 , H01L21/331 , H01L21/31 , H01L21/3205 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/28202 , H01L29/518
摘要： A method for adjusting the amount of doped nitride ions in a dielectric layer so that the nitride ions form bonds with silicon to increase the quality of an oxide layer. The method comprises the step of providing a silicon substrate. Next, a rapid thermal oxidation or furnace oxidation method is used to form an oxide layer over the silicon substrate. Gaseous mixtures having different ratios of nitrogen monoxide, nitrous oxide or ammonia to oxygen are concocted and then allowed to react at different reacting temperatures for controlling the nitride concentration level in the oxide layer. The nitride-doped oxide layer not only can stop the penetration of boron ions, but can also provide a stabilizing effect on the oxide layer/silicon substrate interface without degradation of electrical property, thereby improving the quality of a transistor.
摘要翻译：一种用于调节介电层中的掺杂氮化物离子的量使得氮化物离子与硅键合以提高氧化物层的质量的方法。该方法包括提供硅衬底的步骤。接下来，使用快速热氧化或炉氧化方法在硅衬底上形成氧化物层。将具有不同比例的一氧化氮，一氧化二氮或氨与氧的气态混合物混合，然后在不同的反应温度下反应，以控制氧化物层中的氮化物浓度水平。氮化物掺杂氧化物层不仅可以阻止硼离子的渗透，而且还可以在氧化物层/硅衬底界面上提供稳定效果，而不会降低电性能，从而提高晶体管的质量。

6. 发明授权

US5959311A Structure of an antenna effect monitor 失效
标题翻译：天线效果监视器的结构
公开(公告)号：US5959311A
公开(公告)日：1999-09-28
申请号：US172459
申请日：1998-10-14
申请人： Hsueh-Hao Shih , Mu-Chun Wang , Juan-Yuan Wu , Water Lur
发明人： Hsueh-Hao Shih , Mu-Chun Wang , Juan-Yuan Wu , Water Lur
IPC分类号： H01L23/485 , H01L23/544 , H01L23/58
CPC分类号： H01L24/05 , H01L22/34 , H01L23/58 , H01L2224/05556 , H01L2924/00014 , H01L2924/01033 , H01L2924/13091 , H01L2924/3011
摘要： An antenna effect monitor includes a transistor formed on a semiconductor substrate. The transistor gate is coupled to a doped polysilicon interconnect layer which is also coupled to an antenna effect monitoring unit. Several metal bonding pads float in an orderly fashion above the doped polysilicon interconnect layer without coupling with each other. Several small metal layers are formed in an orderly fashion above the doped polysilicon interconnect layer but are electrically coupled together by several via plugs in between. The top small metal layer is coupled to the top bonding pad. The bottom small metal layer is electrically coupled to the doped polysilicon interconnect layer. Then a passivation layer covers the substrate but leaves a pad opening to expose the top bonding pad.
摘要翻译：天线效应监视器包括形成在半导体衬底上的晶体管。晶体管栅极耦合到掺杂的多晶硅互连层，其也耦合到天线效应监测单元。几个金属接合焊盘在掺杂多晶硅互连层上方有序地浮动，而不会彼此耦合。几个小金属层以有序的方式形成在掺杂多晶硅互连层上方，但是通过其间的几个通孔电连接在一起。顶部小金属层耦合到顶部焊盘。底部小金属层电耦合到掺杂多晶硅互连层。然后钝化层覆盖衬底，但留下衬垫开口以露出顶部焊盘。

7. 发明申请

US20060134863A1 Methods for reducing wordline sheet resistance 有权
标题翻译：减少字幕电阻的方法
公开(公告)号：US20060134863A1
公开(公告)日：2006-06-22
申请号：US11015154
申请日：2004-12-17
申请人： Hung-Wei Liu , Hsueh-Hao Shih , Szu-Yu Wang
发明人： Hung-Wei Liu , Hsueh-Hao Shih , Szu-Yu Wang
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28525 , H01L21/28273 , H01L21/28282 , H01L21/28518 , H01L29/42324 , H01L29/4234
摘要： The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A second poly-Si portion is deposited using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is deposited using silane gas. Wordlines are formed in trenches from poly-Si and WSix. A gate electrode is implanted.
摘要翻译：本发明涉及形成具有相对较低的薄层电阻的记忆字线。在一个实施例中，使用第一前体气体流速将第一多晶硅部分沉积在半导体衬底上。使用第二前体气体流速沉积第二多晶硅部分，其中第二前体流速高于第一前体气体流速。使用硅烷气体沉积硅化钨层。字沟形成于poly-Si和WSix的沟槽中。植入栅电极。

8. 发明授权

US06887757B2 Method of manufacturing flash memory 有权
标题翻译：闪存制造方法
公开(公告)号：US06887757B2
公开(公告)日：2005-05-03
申请号：US10249867
申请日：2003-05-14
申请人： Kuang-Chao Chen , Hsueh-Hao Shih , Ling-Wuu Yang
发明人： Kuang-Chao Chen , Hsueh-Hao Shih , Ling-Wuu Yang
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a flash memory device is provided. First, a substrate partitioned into a memory cell region and a peripheral circuit region is provided. A tunnel dielectric layer is formed over the memory cell region and a liner layer is formed over the peripheral circuit region. Thereafter, a patterned gate conductive layer is formed over the substrate. An inter-gate dielectric layer and a passivation layer are sequentially formed over the substrate. The passivation layer, the inter-gate dielectric layer, the gate conductive layer and the liner layer over the peripheral circuit region are removed. A gate dielectric layer is formed over the peripheral circuit region while the passivation layer over the memory cell region is converted into an oxide layer. Another conductive layer is formed over the substrate. The conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region are patterned to form a memory gate. The second conductive layer over the peripheral circuit region is similarly patterned to form a gate.
摘要翻译：提供一种制造闪速存储器件的方法。首先，提供分割为存储单元区域和外围电路区域的基板。在存储单元区域上形成隧道介电层，并在外围电路区域上形成衬垫层。此后，在衬底上形成图案化的栅极导电层。栅极间电介质层和钝化层依次形成在衬底上。外围电路区域上的钝化层，栅极间电介质层，栅极导电层和衬垫层被去除。在外围电路区域上形成栅极电介质层，同时将存储单元区域上的钝化层转换成氧化物层。在衬底上形成另一导电层。将存储单元区域上的导电层，氧化物层，栅极间电介质层和栅极导电层图案化以形成存储栅极。外围电路区域上的第二导电层类似地构图形成栅极。

9. 再颁专利

USRE40113E1 Method for fabricating gate oxide 有权
标题翻译：制造栅极氧化物的方法
公开(公告)号：USRE40113E1
公开(公告)日：2008-02-26
申请号：US10246826
申请日：2002-09-17
申请人： Yu-Shan Tai , H. T. Yang , Hsueh-Hao Shih , Kuen-Chu Chen
发明人： Yu-Shan Tai , H. T. Yang , Hsueh-Hao Shih , Kuen-Chu Chen
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/28211 , H01L21/31675
摘要： A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about 6-12 6-20 times of the volume of the additional moisture. The method according to the invention improves the electrical quality of the gate oxide by raising the Qbd and by reducing the leakage current of the gate oxide.
摘要翻译：一种制造栅极氧化物的方法包括具有额外氮和水分的稀释湿式氧化方法以及与氮气气体的退火处理，其中附加氮的体积约为<△delete-start id =“DEL-S-00001”的日期 =“20080226”？> 6-12 <？delete-end id =“DEL-S-00001”？> <？insert-start id =“INS-S-00001”date =“20080226”？> 6-20 < ？insert-end id =“INS-S-00001”？>附加水分体积的倍数。根据本发明的方法通过提高栅极氧化物的栅极氧化物的电气质量和通过减小栅极氧化物的漏电流来改善电气质量。

10. 发明授权

US06911374B2 Fabrication method for shallow trench isolation region 有权
标题翻译：浅沟槽隔离区的制作方法
公开(公告)号：US06911374B2
公开(公告)日：2005-06-28
申请号：US10604615
申请日：2003-08-05
申请人： Chin Hsiang Lin , Chin-Wei Liao , Hsueh-Hao Shih , Kuang-Chao Chen
发明人： Chin Hsiang Lin , Chin-Wei Liao , Hsueh-Hao Shih , Kuang-Chao Chen
IPC分类号： H01L21/762 , H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76232 , H01L21/31111 , H01L21/31155
摘要： A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation layer. The surface treated layer is then removed, followed by forming a second insulation layer on the first insulation layer and filling the trench to form a shallow trench isolation region. Since a part of the trench is first filled with the first insulation layer, followed by removing a portion of the first insulation layer, the aspect ratio of the trench is lower before the filling of the second insulation in the trench. The adverse result, such as, void formation in the shallow trench isolation region due to a high aspect ratio, is thus prevented.
摘要翻译：描述了浅沟槽隔离区域的制造方法。沟槽的一部分填充有第一绝缘层，随后进行表面处理工艺以在第一绝缘层的一部分的表面上形成表面处理层。然后去除表面处理层，随后在第一绝缘层上形成第二绝缘层，并填充沟槽以形成浅沟槽隔离区域。由于沟槽的一部分首先填充有第一绝缘层，接着除去第一绝缘层的一部分，沟槽的纵横比在填充沟槽中的第二绝缘体之前较低。因此防止由于高纵横比而导致浅沟槽隔离区域中的空隙形成的不良结果。

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