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1. 发明申请

US20140094009A1 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS 有权
标题翻译：具有自对准互连的半导体器件
公开(公告)号：US20140094009A1
公开(公告)日：2014-04-03
申请号：US14106100
申请日：2013-12-13
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Hung Cho Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Hung Cho Wang
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括金属氧化物器件的衬底。金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。第一和第二掺杂区掺杂有第一类掺杂剂。第一掺杂区具有与第二掺杂区不同的掺杂浓度。金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。源区和漏区掺杂有第二类掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

2. 发明授权

US08610220B2 Semiconductor device with self-aligned interconnects 有权
标题翻译：具有自对准互连的半导体器件
公开(公告)号：US08610220B2
公开(公告)日：2013-12-17
申请号：US13472890
申请日：2012-05-16
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括金属氧化物器件的衬底。金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。第一和第二掺杂区掺杂有第一类掺杂剂。第一掺杂区具有与第二掺杂区不同的掺杂浓度。金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。源区和漏区掺杂有第二类掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

3. 发明申请

US20130307080A1 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS 有权
标题翻译：具有自对准互连的半导体器件
公开(公告)号：US20130307080A1
公开(公告)日：2013-11-21
申请号：US13472890
申请日：2012-05-16
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
IPC分类号： H01L27/088 , H01L21/04
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括金属氧化物器件的衬底。金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。第一和第二掺杂区掺杂有第一类掺杂剂。第一掺杂区具有与第二掺杂区不同的掺杂浓度。金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。源区和漏区掺杂有第二类掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

4. 发明授权

US08930866B2 Method of converting between non-volatile memory technologies and system for implementing the method 有权
标题翻译：在非易失性存储器技术之间转换的方法和用于实现该方法的系统
公开(公告)号：US08930866B2
公开(公告)日：2015-01-06
申请号：US13794024
申请日：2013-03-11
申请人： Hung-Cheng Sung , Yue-Der Chih , Chia-Hsing Chen
发明人： Hung-Cheng Sung , Yue-Der Chih , Chia-Hsing Chen
IPC分类号： G06F17/50 , H01L29/66
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5077 , G06F2217/06 , G06F2217/78 , H01L27/0207 , H01L27/11531 , H01L27/11573 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.
摘要翻译：一种设计电荷俘获存储器阵列的方法，包括设计浮栅存储器阵列布局。浮动栅极存储器布局包括第一类型的晶体管，浮动栅极存储器阵列布局的存储器单元之间的电连接，第一输入/输出（I / O）接口，第一类型的电荷泵和I / O块。该方法还包括使用处理器来修改浮动栅极存储器阵列布局，以用与第一类型的晶体管不同的第二类型的晶体管代替第一类型的晶体管。该方法还包括确定I / O块和第二类型的晶体管之间的工作电压差。该方法还包括使用处理器修改浮动栅极存储器阵列布局，以基于所确定的工作电压差来修改第一电荷泵。

5. 发明授权

US07557402B2 High write and erase efficiency embedded flash cell 有权
标题翻译：高写入和擦除效率嵌入式闪存单元
公开(公告)号：US07557402B2
公开(公告)日：2009-07-07
申请号：US11599930
申请日：2006-11-15
申请人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
发明人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
IPC分类号： H01L29/34
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.
摘要翻译：一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间的结构中的源极区域，源极植入物并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。还提供了一种形成嵌入式闪存单元结构的方法。

6. 发明授权

US07335941B2 Uniform channel programmable erasable flash EEPROM 有权
标题翻译：统一通道可编程可擦除闪存EEPROM
公开(公告)号：US07335941B2
公开(公告)日：2008-02-26
申请号：US10890673
申请日：2004-07-14
申请人： Te-Hsun Hsu , Hung-Cheng Sung
发明人： Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a first dielectric layer with an electronic-trapping layer therebetween. A masking layer is deposited overlying the film. The masking layer and the film are patterned to expose a part of the substrate and to form a floating gate electrode comprising the electronic-trapping layer. An oxide layer is grown overlying the exposed part of the substrate. The masking layer is removed. A conductive layer is deposited overlying the oxide layer and the second dielectric layer. The conductive layer and the oxide layer are patterned to complete a control gate electrode comprising the conductive layer. The control gate electrode has a first part overlying the floating gate electrode and a second part not overlying the floating gate electrode.
摘要翻译：实现了在制造集成电路器件中形成用于闪存器件的分离栅极的新方法。该方法包括提供基底。覆盖在衬底上的膜被沉积。膜包括覆盖在第一电介质层之间的电子捕获层的第二电介质层。掩模层沉积在膜上。图案化掩模层和膜以暴露基板的一部分并形成包括电子捕获层的浮栅电极。生长在衬底的暴露部分上的氧化物层。去除掩模层。沉积覆盖氧化物层和第二介电层的导电层。图案化导电层和氧化物层以完成包括导电层的控制栅电极。控制栅电极具有覆盖浮置栅电极的第一部分和不覆盖浮置栅电极的第二部分。

7. 发明授权

US07326994B2 Logic compatible non-volatile memory cell 有权
标题翻译：逻辑兼容的非易失性存储单元
公开(公告)号：US07326994B2
公开(公告)日：2008-02-05
申请号：US11248357
申请日：2005-10-12
申请人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
发明人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.
摘要翻译：提供了一种非易失性存储单元及其制造方法。非易失性存储单元包括半导体衬底，半导体衬底上的浮置栅极，第一，第二和第三电容器，每个电容器具有第一板并且共用公共浮置栅极作为第二板。非易失性存储单元还包括与第一电容器串联连接的晶体管。晶体管的栅电极连接到存储器阵列的字线，源极/漏极区连接到位线。

8. 发明申请

US20070063248A1 High write and erase efficiency embedded flash cell 有权
标题翻译：高写入和擦除效率嵌入式闪存单元
公开(公告)号：US20070063248A1
公开(公告)日：2007-03-22
申请号：US11599930
申请日：2006-11-15
申请人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
发明人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.
摘要翻译：一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间的结构中的源极区域，源极植入物并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。还提供了一种形成嵌入式闪存单元结构的方法。

9. 发明授权

US07001809B2 Method to increase coupling ratio of source to floating gate in split-gate flash 失效
公开(公告)号：US07001809B2
公开(公告)日：2006-02-21
申请号：US10119327
申请日：2002-04-09
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7885
摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

10. 发明授权

US06878986B2 Embedded flash memory cell having improved programming and erasing efficiency 有权
标题翻译：嵌入式闪存单元具有改进的编程和擦除效率
公开(公告)号：US06878986B2
公开(公告)日：2005-04-12
申请号：US10403137
申请日：2003-03-31
申请人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
发明人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A memory cell including a substrate having a source region; a floating gate structure disposed over the substrate and associated with the source region; and a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source region. The flash memory cell can be fabricated in a method including the steps of forming the floating gate structure over a substrate; forming the source coupling enhancement structure on an exposed portion of the floating gate structure; and forming the source region in the substrate.
摘要翻译：一种存储单元，包括具有源极区域的衬底; 浮置栅极结构，设置在所述衬底上并与所述源极区域相关联; 以及源耦合增强结构，其覆盖所述浮栅结构的暴露部分并延伸到所述源极区。闪存单元可以以包括以下步骤的方法制造：在衬底上形成浮置栅极结构; 在所述浮动栅极结构的暴露部分上形成所述源耦合增强结构; 以及在衬底中形成源区。

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