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1. 发明申请

US20140094009A1 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS 有权
标题翻译：具有自对准互连的半导体器件
公开(公告)号：US20140094009A1
公开(公告)日：2014-04-03
申请号：US14106100
申请日：2013-12-13
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Hung Cho Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Hung Cho Wang
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括金属氧化物器件的衬底。金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。第一和第二掺杂区掺杂有第一类掺杂剂。第一掺杂区具有与第二掺杂区不同的掺杂浓度。金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。源区和漏区掺杂有第二类掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

2. 发明申请

US20130277745A1 ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE 有权
标题翻译：静电放电（ESD）防护环保护结构
公开(公告)号：US20130277745A1
公开(公告)日：2013-10-24
申请号：US13452991
申请日：2012-04-23
申请人： Tsung-Che TSAI , Jam-Wem LEE , Yi-Feng CHANG
发明人： Tsung-Che TSAI , Jam-Wem LEE , Yi-Feng CHANG
IPC分类号： H01L27/06
CPC分类号： H01L27/0259 , H01L21/761 , H01L27/0277 , H01L27/0629
摘要： An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.
摘要翻译： ESD保护电路分别包括第一类型的MOS晶体管，第二类型的MOS晶体管，第二类型的MOS晶体管，I / O焊盘以及第一，第二和第一类型的第一，第二和第三保护环。第一类型的MOS晶体管具有耦合到具有第一电压的第一节点的源极和耦合到第二节点的漏极。第二类型的MOS晶体管具有耦合到第二节点的漏极，以及耦合到具有低于第一电压的第二电压的第三节点的源极。 I / O焊盘耦合到第二节点。第一，第二和第三保护环围绕第二类型的MOS晶体管定位。

3. 发明授权

US08610220B2 Semiconductor device with self-aligned interconnects 有权
标题翻译：具有自对准互连的半导体器件
公开(公告)号：US08610220B2
公开(公告)日：2013-12-17
申请号：US13472890
申请日：2012-05-16
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括金属氧化物器件的衬底。金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。第一和第二掺杂区掺杂有第一类掺杂剂。第一掺杂区具有与第二掺杂区不同的掺杂浓度。金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。源区和漏区掺杂有第二类掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

4. 发明授权

US08963200B2 Methods and apparatus for increased holding voltage in silicon controlled rectifiers for ESD protection 有权
标题翻译：用于ESD保护的可控硅整流器中增加保持电压的方法和装置
公开(公告)号：US08963200B2
公开(公告)日：2015-02-24
申请号：US13527833
申请日：2012-06-20
申请人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
发明人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
IPC分类号： H01L29/45
CPC分类号： H01L27/0262 , H01L21/8248 , H01L23/60 , H01L23/62 , H01L27/0921 , H01L29/0619 , H01L29/73 , H01L29/812
摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.
摘要翻译：提高保持电压SCR的方法和装置。半导体器件包括第一导电类型的半导体衬底; 第一导电类型的第一井; 与第一阱相邻的第二导电类型的第二阱，形成p-n结的第一阱和第二阱的交点; 第一导电类型的第一扩散区域形成在第一阱处并且耦合到接地端子; 形成在第一阱处的第二导电类型的第一扩散区域; 第二导电类型的第二扩散区域形成在第二阱处并耦合到焊盘端子; 第二导电类型的第二扩散区形成在第二阱中; 以及与第二导电类型的第一扩散区相邻形成的与肖特基结相连的接地端子。公开了用于形成装置的方法。

5. 发明申请

US20130341676A1 Methods and Apparatus for Increased Holding Voltage in Silicon Controlled Rectifiers for ESD Protection 有权
公开(公告)号：US20130341676A1
公开(公告)日：2013-12-26
申请号：US13527833
申请日：2012-06-20
申请人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
发明人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L27/0262 , H01L21/8248 , H01L23/60 , H01L23/62 , H01L27/0921 , H01L29/0619 , H01L29/73 , H01L29/812
摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

6. 发明申请

US20130307080A1 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS 有权
标题翻译：具有自对准互连的半导体器件
公开(公告)号：US20130307080A1
公开(公告)日：2013-11-21
申请号：US13472890
申请日：2012-05-16
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
IPC分类号： H01L27/088 , H01L21/04
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括金属氧化物器件的衬底。金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。第一和第二掺杂区掺杂有第一类掺杂剂。第一掺杂区具有与第二掺杂区不同的掺杂浓度。金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。源区和漏区掺杂有第二类掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

7. 发明授权

US08587071B2 Electrostatic discharge (ESD) guard ring protective structure 有权
标题翻译：静电放电（ESD）保护环保护结构
公开(公告)号：US08587071B2
公开(公告)日：2013-11-19
申请号：US13452991
申请日：2012-04-23
申请人： Tsung-Che Tsai , Jam-Wem Lee , Yi-Feng Chang
发明人： Tsung-Che Tsai , Jam-Wem Lee , Yi-Feng Chang
IPC分类号： H01L23/62
CPC分类号： H01L27/0259 , H01L21/761 , H01L27/0277 , H01L27/0629
摘要： An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.
摘要翻译： ESD保护电路分别包括第一类型的MOS晶体管，第二类型的MOS晶体管，第二类型的MOS晶体管，I / O焊盘以及第一，第二和第一类型的第一，第二和第三保护环。第一类型的MOS晶体管具有耦合到具有第一电压的第一节点的源极和耦合到第二节点的漏极。第二类型的MOS晶体管具有耦合到第二节点的漏极，以及耦合到具有低于第一电压的第二电压的第三节点的源极。 I / O焊盘耦合到第二节点。第一，第二和第三保护环围绕第二类型的MOS晶体管定位。

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