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1. 发明申请

US20130277745A1 ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE 有权
标题翻译：静电放电（ESD）防护环保护结构
公开(公告)号：US20130277745A1
公开(公告)日：2013-10-24
申请号：US13452991
申请日：2012-04-23
申请人： Tsung-Che TSAI , Jam-Wem LEE , Yi-Feng CHANG
发明人： Tsung-Che TSAI , Jam-Wem LEE , Yi-Feng CHANG
IPC分类号： H01L27/06
CPC分类号： H01L27/0259 , H01L21/761 , H01L27/0277 , H01L27/0629
摘要： An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.
摘要翻译： ESD保护电路分别包括第一类型的MOS晶体管，第二类型的MOS晶体管，第二类型的MOS晶体管，I / O焊盘以及第一，第二和第一类型的第一，第二和第三保护环。第一类型的MOS晶体管具有耦合到具有第一电压的第一节点的源极和耦合到第二节点的漏极。第二类型的MOS晶体管具有耦合到第二节点的漏极，以及耦合到具有低于第一电压的第二电压的第三节点的源极。 I / O焊盘耦合到第二节点。第一，第二和第三保护环围绕第二类型的MOS晶体管定位。

2. 发明申请

US20130093010A1 High-Voltage Mosfets Having Current Diversion Region in Substrate Near Fieldplate 有权
标题翻译：高压滤波器在底板附近有电流导流区域
公开(公告)号：US20130093010A1
公开(公告)日：2013-04-18
申请号：US13271342
申请日：2011-10-12
申请人： Yun-Pei Huang , Yi-Feng Chang , Jam-Wem Lee
发明人： Yun-Pei Huang , Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/0653 , H01L29/063 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/7816
摘要： To limit or prevent current crowding, various HV-MOSFET embodiments include a current diversion region disposed near a drain region of an HV-MOSFET and near an upper surface of the semiconductor substrate. In some embodiments, the current diversion region is disposed near a field plate of the HV-MOSFET, wherein the field plate can also help to reduce or “smooth” electric fields near the drain to help limit current crowding. In some embodiments, the current diversion region is a p-doped, n-doped, or intrinsic region that is at a floating voltage potential. This current diversion region can push current deeper into the substrate of the HV-MOSFET (relative to conventional HV-MOSFETs), thereby reducing current crowding during ESD events. By reducing current crowding, the current diversion region makes the HV-MOSFETs disclosed herein more impervious to ESD events and, therefore, more reliable in real-world applications.
摘要翻译：为了限制或防止电流拥挤，各种HV-MOSFET实施例包括设置在HV-MOSFET的漏极区附近并且在半导体衬底的上表面附近的电流分流区域。在一些实施例中，电流引流区域设置在HV-MOSFET的场板附近，其中场板还可以帮助减少或“平滑”漏极附近的电场，以帮助限制电流拥挤。在一些实施例中，电流分流区域是处于浮置电压电位的p掺杂，n掺杂或本征区域。该电流分流区可以将电流深度推入HV-MOSFET的衬底（相对于传统HV-MOSFET），从而减少ESD事件期间的电流拥挤。通过减少电流拥挤，电流分流区域使得本文公开的HV-MOSFET更加不可避免地存在ESD事件，因此在现实世界的应用中更可靠。

3. 发明授权

US08331068B2 ESD protection for FinFETs 有权
标题翻译： FinFET的ESD保护
公开(公告)号：US08331068B2
公开(公告)日：2012-12-11
申请号：US12610960
申请日：2009-11-02
申请人： Jam-Wem Lee , Andy Lo
发明人： Jam-Wem Lee , Andy Lo
IPC分类号： H02H3/22 , H02H3/20 , H02H9/04
CPC分类号： H02H9/04 , H01L27/0251 , H01L27/0924 , H01L29/785
摘要： An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor.
摘要翻译：一个实施例是一种半导体器件，包括一个包括鳍状场效应晶体管（FinFET）的接收器电路，一个包括FinFET的收发器电路，以及一个电耦合接收器电路和收发器电路的发送总线，其中接收器电路和收发器电路每个还包括静电放电保护电路包括电耦合到发送总线的平面晶体管。其他实施例还可以包括电耦合第一电力总线和第一接地总线的功率钳，电耦合第二电力总线和第二接地总线的功率钳，或者电耦合第一接地总线和第二地面巴士。此外，收发器电路和接收器电路的平面晶体管可以各自包括平面PMOS晶体管和平面NMOS晶体管。

4. 发明授权

US08049250B2 Circuit and method for power clamp triggered dual SCR ESD protection 有权
标题翻译：用于电源钳位的电路和方法触发双SCR ESD保护
公开(公告)号：US08049250B2
公开(公告)日：2011-11-01
申请号：US12258946
申请日：2008-10-27
申请人： Ming-Hsiang Song , Jam-Wem Lee
发明人： Ming-Hsiang Song , Jam-Wem Lee
IPC分类号： H01L29/66
CPC分类号： H01L29/7436 , H01L27/0262
摘要： Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.
摘要翻译： RC电源钳位电路和方法触发双SCR ESD保护。在集成电路中，受保护的焊盘耦合到上部SCR电路和下部SCR电路; 并且两者耦合到耦合在正电压源和接地电压源之间的RC功率钳位电路。公开了一种用于ESD保护的结构，其具有与第二导电类型的第二阱相邻的第一导电类型的第一阱，形成p-n结的边界以及电耦合到焊盘端子的每个阱中的焊盘接触扩散区; 在焊盘接触扩散区域附近提供附加的扩散，并且与焊接接触扩散区域电隔离，扩散区域和第一和第二阱形成两个SCR器件。这些SCR器件在ESD事件期间被RC功率钳位电路注入到各个阱中的电流被触发。

5. 发明申请

US20100296213A1 ESD Protection for FinFETs 有权
标题翻译： FinFET的ESD保护
公开(公告)号：US20100296213A1
公开(公告)日：2010-11-25
申请号：US12610960
申请日：2009-11-02
申请人： Jam-Wem Lee , Andy Lo
发明人： Jam-Wem Lee , Andy Lo
IPC分类号： H02H9/00 , H01L21/00 , H02H3/22 , H01L27/02
CPC分类号： H02H9/04 , H01L27/0251 , H01L27/0924 , H01L29/785
摘要： An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor.
摘要翻译：一个实施例是一种半导体器件，包括一个包括鳍状场效应晶体管（FinFET）的接收器电路，一个包括FinFET的收发器电路，以及一个电耦合接收器电路和收发器电路的发送总线，其中接收器电路和收发器电路各自还包括静电放电保护电路包括电耦合到发送总线的平面晶体管。其他实施例还可以包括电耦合第一电力总线和第一接地总线的功率钳，电耦合第二电力总线和第二接地总线的功率钳，或者电耦合第一接地总线和第二地面巴士。此外，收发器电路和接收器电路的平面晶体管可以各自包括平面PMOS晶体管和平面NMOS晶体管。

6. 发明申请

US20100103570A1 Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection 有权
标题翻译：电源钳位触发双SCR ESD保护的电路和方法
公开(公告)号：US20100103570A1
公开(公告)日：2010-04-29
申请号：US12258946
申请日：2008-10-27
申请人： Ming-Hsiang Song , Jam-Wem Lee
发明人： Ming-Hsiang Song , Jam-Wem Lee
IPC分类号： H02H9/00 , H01L29/74
CPC分类号： H01L29/7436 , H01L27/0262
摘要： Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.
摘要翻译： RC电源钳位电路和方法触发双SCR ESD保护。在集成电路中，受保护的焊盘耦合到上部SCR电路和下部SCR电路; 并且两者耦合到耦合在正电压源和接地电压源之间的RC功率钳位电路。公开了一种用于ESD保护的结构，其具有与第二导电类型的第二阱相邻的第一导电类型的第一阱，形成p-n结的边界以及电耦合到焊盘端子的每个阱中的焊盘接触扩散区; 在焊盘接触扩散区域附近提供附加的扩散，并且与焊接接触扩散区域电隔离，扩散区域和第一和第二阱形成两个SCR器件。这些SCR器件在ESD事件期间被RC功率钳位电路注入到各个阱中的电流被触发。

7. 发明授权

US09356012B2 High voltage ESD protection apparatus 有权
标题翻译：高压ESD保护装置
公开(公告)号：US09356012B2
公开(公告)日：2016-05-31
申请号：US13243688
申请日：2011-09-23
申请人： Yi-Feng Chang , Jam-Wem Lee
发明人： Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L27/02
CPC分类号： H01L27/0259 , H01L23/50 , H01L27/0255 , H01L27/067 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/7302
摘要： An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus.
摘要翻译： ESD保护装置包括形成在晶体管的发射极上的金属触点。金属触点具有与发射极不同的导电类型。此外，晶体管的金属接触和发射极形成与晶体管串联连接的二极管。与晶体管串联连接的二极管为ESD保护装置的击穿电压提供了额外的余量。

8. 发明授权

US08937364B2 Multi-gate high voltage device 有权
标题翻译：多门高压器件
公开(公告)号：US08937364B2
公开(公告)日：2015-01-20
申请号：US13920913
申请日：2013-06-18
申请人： Jam-Wem Lee
发明人： Jam-Wem Lee
IPC分类号： H01L29/02 , H03K17/687
CPC分类号： H01L27/088 , H01L27/0207 , H01L29/0653 , H01L29/1095 , H01L29/7816 , H01L29/7831 , H03K17/687 , H03K2017/6878
摘要： A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.
摘要翻译：本公开中提供了一种高电压半导体器件，特别是包括在栅极和漏极之间具有共同漏极，第一阱和绝缘结构的多个高击穿电压晶体管的器件以及其使用方法。器件中的高击穿电压晶体管一起处于椭圆形状。第二阱区域，栅极结构和源极区域是在顶视图中具有至少两个不连续或开口的部分重叠的不连续的椭圆环。相应的不连续或开口限定每个高击穿电压晶体管。

9. 发明授权

US08853825B2 ESD protection apparatus 有权
标题翻译： ESD保护装置
公开(公告)号：US08853825B2
公开(公告)日：2014-10-07
申请号：US13246672
申请日：2011-09-27
申请人： Jam-Wem Lee , Yi-Feng Chang
发明人： Jam-Wem Lee , Yi-Feng Chang
IPC分类号： H01L27/082 , H01L29/732 , H01L27/02 , H01L29/06
CPC分类号： H01L27/0259 , H01L29/0649 , H01L29/732 , H01L29/735
摘要： An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region.
摘要翻译： ESD保护装置包括在基板上形成的基板，低电压p型阱和低电压n型阱。 ESD保护装置还包括形成在低电压p型阱上的第一P +区和形成在低电压n型阱上的第二P +区。第一P +区和第二P +区被第一隔离区隔开。 ESD保护装置的击穿电压可以通过调整第一隔离区域的长度来调节。

10. 发明授权

US08841696B2 High-trigger current SCR 有权
标题翻译：高触发电流SCR
公开(公告)号：US08841696B2
公开(公告)日：2014-09-23
申请号：US13459283
申请日：2012-04-30
申请人： Jam-Wem Lee , Yi-Feng Chang
发明人： Jam-Wem Lee , Yi-Feng Chang
IPC分类号： H01L23/36
CPC分类号： H01L29/7436 , H01L27/0262
摘要： An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.
摘要翻译： SCR包括具有第一掺杂浓度的第一类型的第一掺杂区域。第一类型的第一阱和第二类型的第一阱被布置在第一类型的第一掺杂区域的上部区域中，使得第二类型的第一阱与第一类型的第一阱横向间隔开，非零距离。第一类型的第二掺杂区域具有大于第一掺杂浓度的第二掺杂浓度，并且设置在第二类型的第一阱中以形成SCR的阳极。第二类型的第一掺杂区域设置在第一类型的第一阱中并形成SCR的阴极。

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