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1. 发明授权

US08838042B2 RF front-end with integrated T/R switch 有权
标题翻译：射频前端集成了T / R开关
公开(公告)号：US08838042B2
公开(公告)日：2014-09-16
申请号：US13107729
申请日：2011-05-13
申请人： Yuan Lu , Renaldi Winoto , Jinho Park , Li Lin , Xinhua Chen , Ming He , David Signoff , Wayne Loeb
发明人： Yuan Lu , Renaldi Winoto , Jinho Park , Li Lin , Xinhua Chen , Ming He , David Signoff , Wayne Loeb
IPC分类号： H04B1/38 , H04B1/48
CPC分类号： H04B1/48 , H04B1/18
摘要： Disclosed is a transmit/receive circuit arrangement wherein a transceiver circuit including a transmit/receive switch is fabricated on an integrated circuit chip. A matching network is wholly disposed off-chip relative to the integrated circuit chip. In embodiments, at least a portion of the matching network is formed off-chip and a portion of the matching network is formed on-chip.
摘要翻译：公开了一种发射/接收电路装置，其中在集成电路芯片上制造包括发射/接收开关的收发器电路。匹配网络相对于集成电路芯片完全设置在片外。在实施例中，匹配网络的至少一部分形成在片外，匹配网络的一部分形成在芯片上。

2. 发明申请

US20110285475A1 RF Front-End with Integrated T/R Switch 有权
标题翻译： RF前端，集成T / R开关
公开(公告)号：US20110285475A1
公开(公告)日：2011-11-24
申请号：US13107729
申请日：2011-05-13
申请人： Yuan Lu , Renaldi Winoto , Jinho Park , Li Lin , Xinhua Chen , Ming He , David Signoff , Wayne Loeb
发明人： Yuan Lu , Renaldi Winoto , Jinho Park , Li Lin , Xinhua Chen , Ming He , David Signoff , Wayne Loeb
IPC分类号： H01P1/15
CPC分类号： H04B1/48 , H04B1/18
摘要： Disclosed is a transmit/receive circuit arrangement wherein a transceiver circuit including a transmit/receive switch is fabricated on an integrated circuit chip. A matching network is wholly disposed off-chip relative to the integrated circuit chip. In embodiments, at least a portion of the matching network is formed off-chip and a portion of the matching network is formed on-chip.
摘要翻译：公开了一种发射/接收电路装置，其中在集成电路芯片上制造包括发射/接收开关的收发器电路。匹配网络相对于集成电路芯片完全设置在片外。在实施例中，匹配网络的至少一部分形成在片外，匹配网络的一部分形成在芯片上。

3. 发明授权

US08638168B1 Digital power amplifier 有权
标题翻译：数字功率放大器
公开(公告)号：US08638168B1
公开(公告)日：2014-01-28
申请号：US13490901
申请日：2012-06-07
申请人： David M. Signoff , Li Lin , Renaldi Winoto , Wayne A. Loeb , Shu-Hsien Liao , Ming He
发明人： David M. Signoff , Li Lin , Renaldi Winoto , Wayne A. Loeb , Shu-Hsien Liao , Ming He
IPC分类号： H03F3/68
CPC分类号： H03F3/68 , H03F1/0244 , H03F3/2175 , H03F3/24
摘要： Systems and methods for power amplification using multiple digital amplifiers are provided. A power amplifier includes a first digital amplifier configured to process a digital input signal to generate a first analog output signal. The first analog output signal is configured to have a magnitude corresponding to amplitude information of the digital input signal. The power amplifier further includes a second digital amplifier configured to process an adjusted digital input signal to generate a second analog output signal. The second analog output signal is configured to have a magnitude corresponding to amplitude information of the adjusted digital input signal. An adjustment module configured to adjust amplitude information and phase information of the digital input signal generates the adjusted digital input signal. The digital input signal is adjusted to control a relationship between the first analog output signal and the second analog output signal.
摘要翻译：提供了使用多个数字放大器进行功率放大的系统和方法。功率放大器包括被配置为处理数字输入信号以产生第一模拟输出信号的第一数字放大器。第一模拟输出信号被配置为具有对应于数字输入信号的振幅信息的幅度。功率放大器还包括第二数字放大器，其被配置为处理经调整的数字输入信号以产生第二模拟输出信号。第二模拟输出信号被配置为具有对应于经调整的数字输入信号的振幅信息的幅度。被配置为调整数字输入信号的幅度信息和相位信息的调整模块生成调整后的数字输入信号。调整数字输入信号以控制第一模拟输出信号和第二模拟输出信号之间的关系。

4. 发明申请

US20140057435A1 METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：在集成电路设备上形成基于铜基导电结构的金属层的方法
公开(公告)号：US20140057435A1
公开(公告)日：2014-02-27
申请号：US13591341
申请日：2012-08-22
申请人： Xunyuan Zhang , Kunaljeet Tanwar , Ming He
发明人： Xunyuan Zhang , Kunaljeet Tanwar , Ming He
IPC分类号： H01L21/768
CPC分类号： H01L21/76849
摘要： Disclosed herein are various methods of forming a metal cap layer on copper-based conductive structures on integrated circuit devices, and integrated circuit devices having such a structure. In one example, the method includes the steps of forming a conductive feature comprised of copper in a layer of insulating material, performing a metal removal process to remove a portion of the conductive feature and thereby define a recess above a residual portion of the copper feature, and performing a selective deposition process to form a cap layer comprised of cobalt, manganese, CoWP or NiWP within the recess.
摘要翻译：本文公开了在集成电路器件上的铜基导电结构上形成金属覆盖层的各种方法，以及具有这种结构的集成电路器件。在一个示例中，该方法包括以下步骤：在绝缘材料层中形成由铜构成的导电特征，执行金属去除工艺以去除导电特征的一部分，从而在铜特征的残余部分上方限定凹陷并且进行选择性沉积工艺以在凹部内形成由钴，锰，CoWP或NiWP组成的覆盖层。

5. 发明授权

US08517769B1 Methods of forming copper-based conductive structures on an integrated circuit device 有权
标题翻译：在集成电路器件上形成铜基导电结构的方法
公开(公告)号：US08517769B1
公开(公告)日：2013-08-27
申请号：US13422295
申请日：2012-03-16
申请人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
发明人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
IPC分类号： H01L21/4763 , H01L21/00
CPC分类号： H01L21/76879 , H01L21/76861 , H01L21/76864 , H01L21/76865 , H01L21/76874 , H01L2924/0002
摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a trench/via in a layer of insulating material, forming a copper-based seed layer above the layer of insulating material and in the trench/via, performing a heating process on the copper-based seed layer to increase an amount of the copper-based seed layer positioned proximate a bottom of the trench/via, performing an etching process on said copper-based seed layer and performing an electroless copper deposition process to fill the trench/via with a copper-based material.
摘要翻译：这里公开了在集成电路器件上形成铜基导电结构的各种方法。在一个示例中，该方法包括以下步骤：在绝缘材料层中形成沟槽/通孔，在绝缘材料层上方和沟槽/通孔中形成铜基种子层，在铜 - 以增加位于沟槽/通孔的底部附近的铜基种子层的量，对所述铜基种子层进行蚀刻工艺，并执行无电镀铜沉积工艺以填充沟槽/通孔铜基材料。

6. 发明申请

US20090037759A1 Clock shifting and prioritization system and method 有权
标题翻译：时钟偏移和优先化系统和方法
公开(公告)号：US20090037759A1
公开(公告)日：2009-02-05
申请号：US11888368
申请日：2007-07-31
申请人： Isaac Lagnado , Ming He , Henry F. Lada
发明人： Isaac Lagnado , Ming He , Henry F. Lada
IPC分类号： G06F1/00
CPC分类号： G06F1/12
摘要： A clock shifting and prioritization method comprising adjusting a frequency for a plurality of clocks corresponding to a plurality of respective components of an electronic device based on a desired user configuration setting for operating the electronic device.
摘要翻译：一种时钟偏移和优先化方法，包括基于用于操作电子设备的期望的用户配置设置调整与电子设备的多个相应组件对应的多个时钟的频率。

7. 发明申请

US20080182531A1 System and method for configuring a wireless module power limit 有权
标题翻译：用于配置无线模块功率限制的系统和方法
公开(公告)号：US20080182531A1
公开(公告)日：2008-07-31
申请号：US11699539
申请日：2007-01-29
申请人： Isaac Lagnado , Ming He
发明人： Isaac Lagnado , Ming He
IPC分类号： H04B1/04 , H04B7/00
CPC分类号： H04W52/52 , H04B2001/0416 , H04W52/367
摘要： A system for configuring a wireless module power limit comprises a wireless module having a control module configured to automatically select a power limit setting from one of a plurality of power limit settings to set a maximum output power level for the wireless module to enable an antenna coupled to the wireless module to radiate at a predetermined power level.
摘要翻译：用于配置无线模块功率限制的系统包括无线模块，其具有控制模块，所述控制模块被配置为从多个功率限制设置中的一个功能限制设置中自动选择功率限制设置，以设置无线模块的最大输出功率电平，以使天线耦合到无线模块以预定功率电平辐射。

8. 发明授权

US06534316B2 Colorimetric and fluorimetric analysis of carbohydrates 有权
标题翻译：碳水化合物的比色和荧光分析
公开(公告)号：US06534316B2
公开(公告)日：2003-03-18
申请号：US09778158
申请日：2001-02-05
申请人： Robert M. Strongin , Larry Allen Cabell , Nadia St. Luce , Patrick T. Lewis , Ming He , Jorge O. Escobedo Cordova , Claude Joseph Davis
发明人： Robert M. Strongin , Larry Allen Cabell , Nadia St. Luce , Patrick T. Lewis , Ming He , Jorge O. Escobedo Cordova , Claude Joseph Davis
IPC分类号： G01N3300
CPC分类号： G01N21/78 , G01N21/64 , Y10T436/142222 , Y10T436/143333 , Y10T436/144444
摘要： Methods are disclosed for the simple, rapid, and selective colorimetric detection of carbohydrates, including fructose, glucose, sialic acid, and oligosaccharides. There is no need for any prior hydrolysis or other chemical modification or of the analytes. Resorcinarenes, xanthene dyes, and related compounds, formally produced by the reaction of 2 equivalents of resorcinol and a suitable electrophilic condensation partner, are used as chromophores or fluorophores for the detection of sugars and other carbohydrates.
摘要翻译：公开了用于简单，快速和选择性比色检测碳水化合物的方法，包括果糖，葡萄糖，唾液酸和寡糖。不需要任何先前的水解或其他化学改性或分析物。使用通过2当量的间苯二酚和合适的亲电子缩合配偶体的反应形成的间苯二酚，呫吨染料和相关化合物作为发色团或荧光团用于检测糖和其它碳水化合物。

9. 发明申请

US20140097538A1 SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM 有权
标题翻译：具有穿过底部的自制障碍层的半导体器件
公开(公告)号：US20140097538A1
公开(公告)日：2014-04-10
申请号：US13648433
申请日：2012-10-10
申请人： Larry Zhao , Ming He , Xunyuan Zhang , Sean Xuan Lin
发明人： Larry Zhao , Ming He , Xunyuan Zhang , Sean Xuan Lin
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76831 , H01L21/76846 , H01L21/76855 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
摘要翻译：提供了一种用于形成半导体器件的方法。通常，通过在金属层上设置金属层，覆盖层和覆盖层上的超低k层来形成器件。然后通过超低k层和盖层形成通孔。一旦形成通孔，就可以选择性地将阻挡层（例如，钴（Co），钽（Ta），钴 - 钨 - 磷化物（CoWP）或能够充当铜（CU）扩散阻挡层的其它金属）通孔的底面。然后将衬垫层（例如锰（MN）或铝（AL））施加到通孔的一组侧壁。然后可以用随后的金属层（具有或不具有种子层）填充通孔，然后可以进一步处理（例如，退火）该器件。

10. 发明授权

US08673766B2 Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition 有权
标题翻译：通过形成具有沉积厚度分布的铜基种子层，然后进行蚀刻工艺和无电镀铜沉积形成铜基导电结构的方法
公开(公告)号：US08673766B2
公开(公告)日：2014-03-18
申请号：US13476692
申请日：2012-05-21
申请人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
发明人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76874 , H01L21/76843 , H01L21/76865 , H01L21/76879
摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material.
摘要翻译：这里公开了在集成电路器件上形成铜基导电结构的各种方法。在一个示例中，该方法包括在绝缘材料层中形成沟槽/通孔，执行沉积工艺以在沟槽/通孔中的绝缘材料层上方形成沉积的基于铜的种子层，其中铜 - 基于晶种的层具有位于沟槽/通孔的底部之上的第一部分，其比位于沟槽/通孔侧壁上方的铜籽晶层的第二部分更厚，对沉积的铜进行蚀刻工艺基本种子层，以基本上去除沉积的铜基种子层的第二部分的部分，并执行无电沉积工艺以用铜基材料填充沟槽/通孔。

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