专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

US20230163564A1 Single-Photon Source Emitting Single-Photon with Controllable Circular Polarization Direction 审中-公开
公开(公告)号：US20230163564A1
公开(公告)日：2023-05-25
申请号：US18100757
申请日：2023-01-24
申请人： Yuan LU
发明人： Yuan LU
IPC分类号： H01S5/06 , H01S5/183
CPC分类号： H01S5/0607 , H01S5/18361
摘要： Disclosed is a single-photon source emitting light with controllable circular polarization direction. A pillar structure above a semiconductor substrate includes a semiconductor single-quantum-dot structure. A spin injection layer is arranged above the pillar structure. A pulsed voltage is applied between the spin injection layer and the semiconductor substrate to inject a spin-polarized single-carrier from the spin injection layer into the semiconductor single-quantum-dot structure. In response to the injected single-carrier, a single-quantum-dot emits a single-photon with a circular polarization direction corresponding to the spin direction of the injected single-carrier. The polarization controllable single-photon source allows to use magnetic or electrical means to modulate the circular polarization direction of single-photon. The modulation speed by electrical mean can reach up to GHz range.

2. 发明申请

US20180146810A1 COOKING MACHINE 审中-公开
公开(公告)号：US20180146810A1
公开(公告)日：2018-05-31
申请号：US15361393
申请日：2016-11-26
申请人： CHEN-YUAN LU
发明人： CHEN-YUAN LU
IPC分类号： A47J27/00 , A47J27/04 , A47J36/06
CPC分类号： A47J27/004 , A47J27/04 , A47J27/12 , A47J2027/043
摘要： A cooking machine includes a body having a room in which a container holder is movably located. The container holder can be moved into or removed out from the room. A heating unit has a first heater which is located in the room and movable to be inserted into a container on the container holder along vertical direction so as to cook food in the container.

3. 发明授权

US09032759B2 Fluid applicator and glass cleaning process 有权
标题翻译：流体涂抹器和玻璃清洗过程
公开(公告)号：US09032759B2
公开(公告)日：2015-05-19
申请号：US13027508
申请日：2011-02-15
申请人： Chih Yuan Lu , Chia Hsien Wu
发明人： Chih Yuan Lu , Chia Hsien Wu
IPC分类号： C03C23/00 , B08B3/02
CPC分类号： B08B3/022 , C03C23/0075
摘要： A fluid applicator (20), for cleaning particles from a glass sheet (2), including a conveyor (40) for supporting the glass sheet, a conveyance plane, and a nozzle (24). The conveyance plane is disposed adjacent the conveyor so that when the glass sheet is conveyed by the conveyor, a surface (6) of the glass sheet is disposed in the conveyance plane. The nozzle has a longitudinal axis (23), wherein the longitudinal axis is disposed at an angle of 30 to 90 degrees with respect to the conveyance plane, and the nozzle is disposed at a distance (21) of less than or equal to 100 mm from the conveyance plane. Also, there is disclosed a method for cleaning particles from a glass sheet, using the fluid applicator. The fluid may be delivered to the nozzle at a pressure of 10 to 80 kg/cm2 and a flow rate of from 1 to 20 l/min.
摘要翻译：一种用于从玻璃板（2）清除颗粒的流体施加器（20），包括用于支撑玻璃板的输送机（40），输送平面和喷嘴（24）。传送平面设置在传送带附近，使得当玻璃板被输送机输送时，玻璃板的表面（6）设置在传送平面中。所述喷嘴具有纵向轴线（23），其中所述纵向轴线相对于输送平面以30至90度的角度设置，并且所述喷嘴设置在小于或等于100mm的距离（21）从运输机。此外，公开了一种使用流体施加器从玻璃板清洁颗粒的方法。流体可以以10至80kg / cm 2的压力和1至20l / min的流速输送到喷嘴。

4. 发明授权

US08759219B2 Planarization method applied in process of manufacturing semiconductor component 有权
标题翻译：在制造半导体元件的过程中应用的平面化方法
公开(公告)号：US08759219B2
公开(公告)日：2014-06-24
申请号：US13012211
申请日：2011-01-24
申请人： Ya-Hsueh Hsieh , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
发明人： Ya-Hsueh Hsieh , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
IPC分类号： H01L21/331 , H01L21/463
CPC分类号： H01L21/7684 , H01L21/3212 , H01L29/4966 , H01L29/517
摘要： A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
摘要翻译：提供了制造半导体部件的平面化方法。介电层形成在衬底之上并在其中限定沟槽。在沟槽中依次形成阻挡层和金属层。通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

5. 发明授权

US08624673B2 Self-biasing radio frequency circuitry 有权
标题翻译：自偏置射频电路
公开(公告)号：US08624673B2
公开(公告)日：2014-01-07
申请号：US13348397
申请日：2012-01-11
申请人： Jinho Park , Yuan Lu , Li Lin
发明人： Jinho Park , Yuan Lu , Li Lin
IPC分类号： H03F3/26
CPC分类号： H03F3/3016 , H03F1/0272 , H03F1/083 , H03F3/195 , H03F3/3028 , H03F2200/294 , H03F2203/30021 , H03F2203/30027 , H03F2203/30031 , H03F2203/30033 , H03F2203/30036 , H03F2203/30084 , H03F2203/30117
摘要： The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit.
摘要翻译：本公开描述了自偏置射频电路。在一些方面中，射频（RF）信号经由具有第一晶体管的电路被放大，该第一晶体管被配置为将电流源电流到电路的输出，以及第二晶体管，被配置为从电路的输出吸收电流，并且提供另一个信号，没有有源电路，从电路的输出到第一晶体管的栅极有效地偏置电路输出处的电压。通过这样做，电路的输出可以被偏置而没有有源电路，这可以降低电路消耗的设计复杂度和衬底面积。

6. 发明授权

US08580641B2 Techniques providing high-k dielectric metal gate CMOS 有权
公开(公告)号：US08580641B2
公开(公告)日：2013-11-12
申请号：US13191297
申请日：2011-07-26
申请人： Wei-Yuan Lu , Kuan-Chung Chen , Chun-Fai Cheng
发明人： Wei-Yuan Lu , Kuan-Chung Chen , Chun-Fai Cheng
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8238 , H01L21/70 , H01L21/8234
CPC分类号： H01L27/11 , H01L21/28176 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L27/1104 , H01L29/0649 , H01L29/4966 , H01L29/511 , H01L29/517 , H01L29/66545 , H01L29/7827
摘要： A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.

7. 发明授权

US08535998B2 Method for fabricating a gate structure 有权
标题翻译：栅极结构的制造方法
公开(公告)号：US08535998B2
公开(公告)日：2013-09-17
申请号：US12720075
申请日：2010-03-09
申请人： Fung Ka Hing , Haiting Wang , Han-Ting Tsai , Chun-Fai Cheng , Wei-Yuan Lu , Hsien-Ching Lo , Kuan-Chung Chen
发明人： Fung Ka Hing , Haiting Wang , Han-Ting Tsai , Chun-Fai Cheng , Wei-Yuan Lu , Hsien-Ching Lo , Kuan-Chung Chen
IPC分类号： H01L21/338
CPC分类号： H01L29/7833 , H01L21/76834 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/7834 , H01L29/7836
摘要： The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.
摘要翻译：本公开公开了一种用于制造栅极结构的示例性方法，其包括在衬底上沉积和图案化虚拟氧化物层和伪栅极电极层; 围绕所述虚拟氧化物层和所述伪栅极电极层，具有牺牲层; 用含氮介电层围绕牺牲层; 用层间介质层包围含氮介电层; 去除所述伪栅电极层; 去除虚拟氧化物层; 去除所述牺牲层以在所述含氮介电层中形成开口; 并沉积栅极电介质; 并沉积栅电极。

8. 发明申请

US20130187221A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20130187221A1
公开(公告)日：2013-07-25
申请号：US13356207
申请日：2012-01-23
申请人： Wei-Yuan Lu , Li-Ping Huang , Han-Ting Tsai , Wei-Ching Wang , Ming-Shuan Li , Hsueh-Jen Yang , Kuan-Chung Chen
发明人： Wei-Yuan Lu , Li-Ping Huang , Han-Ting Tsai , Wei-Ching Wang , Ming-Shuan Li , Hsueh-Jen Yang , Kuan-Chung Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7849 , B82Y10/00 , H01L21/26506 , H01L21/324 , H01L29/32 , H01L29/6653 , H01L29/6656 , H01L29/7613 , H01L29/7843 , H01L29/7848
摘要： A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.
摘要翻译：形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。该方法还包括在衬底上形成第一应力膜。该方法还包括对基板和第一应力膜执行第一退火处理。该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。

9. 发明申请

US20130062312A1 Non-Contact Etching of Moving Glass Sheets 失效
标题翻译：移动玻璃板非接触蚀刻
公开(公告)号：US20130062312A1
公开(公告)日：2013-03-14
申请号：US13671883
申请日：2012-11-08
申请人： Gautam Narendra Kudva , Chih Yuan Lu , Weiwei Luo , Yoshihiro Nakamura , Tetsuzou Yamada
发明人： Gautam Narendra Kudva , Chih Yuan Lu , Weiwei Luo , Yoshihiro Nakamura , Tetsuzou Yamada
IPC分类号： C03C15/00
CPC分类号： C03C15/00 , Y10T428/24355
摘要： Methods and apparatus are disclosed for etching flexible glass sheets (13) in which the sheets (13) are transported in a near vertical orientation past non-contact, liquid-ejecting bearings (3) which apply an etching solution (e.g., an aqueous NaF/H3PO4 solution) to the sheets (13). In certain embodiments, the uppermost liquid-ejecting bearing (3) is above the top edge of the sheet (13) and thus is able to apply etching solution to the top of the sheet. In other embodiments, a top shower (11), which includes a set of spray nozzles (21) located above and distributed along the length of the apparatus, is used to apply etching solution to the top of the sheet (13). Using the disclosed methods and apparatus, glass sheets (13) produced by a fusion process are provided which have areas greater than five square meters and average surface roughness values in the range of 0.5 nanometers to 1.1 nanometers.
摘要翻译：公开了用于蚀刻柔性玻璃板（13）的方法和装置，其中片材（13）以接近垂直的方向输送通过非接触的液体喷射轴承（3），该轴承（3）施加蚀刻溶液（例如，NaF / H 3 PO 4溶液）。在某些实施例中，最上面的液体喷射轴承（3）在片材（13）的顶部边缘之上，因此能够将蚀刻溶液施加到片材的顶部。在其它实施例中，使用顶部喷淋器（11），其包括位于设备上方并沿着设备长度分布的一组喷嘴（21），以将蚀刻溶液施加到片材（13）的顶部。使用所公开的方法和装置，提供了通过熔融方法生产的玻璃板（13），其具有大于5平方米的面积，并且在0.5纳米至1.1纳米的范围内的平均表面粗糙度值。

10. 发明申请

US20120187563A1 PLANARIZATION METHOD APPLIED IN PROCESS OF MANUFACTURING SEMICONDUCTOR COMPONENT 有权
标题翻译：应用于制造半导体元件的方法的平面化方法
公开(公告)号：US20120187563A1
公开(公告)日：2012-07-26
申请号：US13012211
申请日：2011-01-24
申请人： Ya-Hsueh HSIEH , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
发明人： Ya-Hsueh HSIEH , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
IPC分类号： H01L23/532 , H01L21/28
CPC分类号： H01L21/7684 , H01L21/3212 , H01L29/4966 , H01L29/517
摘要： A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
摘要翻译：提供了制造半导体部件的平面化方法。介电层形成在衬底之上并在其中限定沟槽。在沟槽中依次形成阻挡层和金属层。通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式