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1. 发明申请

US20130309863A1 METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION 有权
标题翻译：通过形成具有沉积厚度剖面的铜基层和形成蚀刻过程和电沉积铜沉积的形成铜基导电结构的方法
公开(公告)号：US20130309863A1
公开(公告)日：2013-11-21
申请号：US13476692
申请日：2012-05-21
申请人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
发明人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
IPC分类号： H01L21/768
CPC分类号： H01L21/76874 , H01L21/76843 , H01L21/76865 , H01L21/76879
摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material.
摘要翻译：这里公开了在集成电路器件上形成铜基导电结构的各种方法。在一个示例中，该方法包括在绝缘材料层中形成沟槽/通孔，执行沉积工艺以在沟槽/通孔中的绝缘材料层上形成沉积的基于铜的种子层，其中铜 - 基于晶种的层具有位于沟槽/通孔的底部之上的第一部分，其比位于沟槽/通孔侧壁上方的铜籽晶层的第二部分更厚，对沉积的铜进行蚀刻工艺基本种子层，以基本上去除沉积的铜基种子层的第二部分的部分，并执行无电沉积工艺以用铜基材料填充沟槽/通孔。

2. 发明授权

US08517769B1 Methods of forming copper-based conductive structures on an integrated circuit device 有权
标题翻译：在集成电路器件上形成铜基导电结构的方法
公开(公告)号：US08517769B1
公开(公告)日：2013-08-27
申请号：US13422295
申请日：2012-03-16
申请人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
发明人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
IPC分类号： H01L21/4763 , H01L21/00
CPC分类号： H01L21/76879 , H01L21/76861 , H01L21/76864 , H01L21/76865 , H01L21/76874 , H01L2924/0002
摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a trench/via in a layer of insulating material, forming a copper-based seed layer above the layer of insulating material and in the trench/via, performing a heating process on the copper-based seed layer to increase an amount of the copper-based seed layer positioned proximate a bottom of the trench/via, performing an etching process on said copper-based seed layer and performing an electroless copper deposition process to fill the trench/via with a copper-based material.
摘要翻译：这里公开了在集成电路器件上形成铜基导电结构的各种方法。在一个示例中，该方法包括以下步骤：在绝缘材料层中形成沟槽/通孔，在绝缘材料层上方和沟槽/通孔中形成铜基种子层，在铜 - 以增加位于沟槽/通孔的底部附近的铜基种子层的量，对所述铜基种子层进行蚀刻工艺，并执行无电镀铜沉积工艺以填充沟槽/通孔铜基材料。

3. 发明授权

US08673766B2 Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition 有权
标题翻译：通过形成具有沉积厚度分布的铜基种子层，然后进行蚀刻工艺和无电镀铜沉积形成铜基导电结构的方法
公开(公告)号：US08673766B2
公开(公告)日：2014-03-18
申请号：US13476692
申请日：2012-05-21
申请人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
发明人： Sean X. Lin , Ming He , Xunyuan Zhang , Larry Zhao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76874 , H01L21/76843 , H01L21/76865 , H01L21/76879
摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material.
摘要翻译：这里公开了在集成电路器件上形成铜基导电结构的各种方法。在一个示例中，该方法包括在绝缘材料层中形成沟槽/通孔，执行沉积工艺以在沟槽/通孔中的绝缘材料层上方形成沉积的基于铜的种子层，其中铜 - 基于晶种的层具有位于沟槽/通孔的底部之上的第一部分，其比位于沟槽/通孔侧壁上方的铜籽晶层的第二部分更厚，对沉积的铜进行蚀刻工艺基本种子层，以基本上去除沉积的铜基种子层的第二部分的部分，并执行无电沉积工艺以用铜基材料填充沟槽/通孔。

4. 发明申请

US20140097538A1 SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM 有权
标题翻译：具有穿过底部的自制障碍层的半导体器件
公开(公告)号：US20140097538A1
公开(公告)日：2014-04-10
申请号：US13648433
申请日：2012-10-10
申请人： Larry Zhao , Ming He , Xunyuan Zhang , Sean Xuan Lin
发明人： Larry Zhao , Ming He , Xunyuan Zhang , Sean Xuan Lin
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76831 , H01L21/76846 , H01L21/76855 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
摘要翻译：提供了一种用于形成半导体器件的方法。通常，通过在金属层上设置金属层，覆盖层和覆盖层上的超低k层来形成器件。然后通过超低k层和盖层形成通孔。一旦形成通孔，就可以选择性地将阻挡层（例如，钴（Co），钽（Ta），钴 - 钨 - 磷化物（CoWP）或能够充当铜（CU）扩散阻挡层的其它金属）通孔的底面。然后将衬垫层（例如锰（MN）或铝（AL））施加到通孔的一组侧壁。然后可以用随后的金属层（具有或不具有种子层）填充通孔，然后可以进一步处理（例如，退火）该器件。

5. 发明授权

US08586473B1 Methods for fabricating integrated circuits with ruthenium-lined copper 有权
标题翻译：用钌衬铜制造集成电路的方法
公开(公告)号：US08586473B1
公开(公告)日：2013-11-19
申请号：US13533816
申请日：2012-06-26
申请人： Kunaljeet Tanwar , Xunyuan Zhang , Ming He
发明人： Kunaljeet Tanwar , Xunyuan Zhang , Ming He
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a dielectric layer defining a plane. In the method, the dielectric layer is etched to form trenches. Then, a ruthenium-containing liner layer is deposited overlying the dielectric layer. The trenches are filled with copper-containing metal. The method includes recessing the copper-containing metal in each trench to form a space between the copper-containing metal and the plane. The space is filled with a capping layer. The layers are then planarized to at least the plane.
摘要翻译：提供了制造集成电路的方法。在一个实施例中，一种用于制造集成电路的方法包括沉积限定平面的电介质层。在该方法中，蚀刻介电层以形成沟槽。然后，沉积覆盖在介电层上的含钌衬里层。沟槽用含铜金属填充。该方法包括在每个沟槽中凹入含铜金属，以在含铜金属和平面之间形成空间。空间填充有覆盖层。然后将这些层平坦化至少至该平面。

6. 发明申请

US20140057435A1 METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：在集成电路设备上形成基于铜基导电结构的金属层的方法
公开(公告)号：US20140057435A1
公开(公告)日：2014-02-27
申请号：US13591341
申请日：2012-08-22
申请人： Xunyuan Zhang , Kunaljeet Tanwar , Ming He
发明人： Xunyuan Zhang , Kunaljeet Tanwar , Ming He
IPC分类号： H01L21/768
CPC分类号： H01L21/76849
摘要： Disclosed herein are various methods of forming a metal cap layer on copper-based conductive structures on integrated circuit devices, and integrated circuit devices having such a structure. In one example, the method includes the steps of forming a conductive feature comprised of copper in a layer of insulating material, performing a metal removal process to remove a portion of the conductive feature and thereby define a recess above a residual portion of the copper feature, and performing a selective deposition process to form a cap layer comprised of cobalt, manganese, CoWP or NiWP within the recess.
摘要翻译：本文公开了在集成电路器件上的铜基导电结构上形成金属覆盖层的各种方法，以及具有这种结构的集成电路器件。在一个示例中，该方法包括以下步骤：在绝缘材料层中形成由铜构成的导电特征，执行金属去除工艺以去除导电特征的一部分，从而在铜特征的残余部分上方限定凹陷并且进行选择性沉积工艺以在凹部内形成由钴，锰，CoWP或NiWP组成的覆盖层。

7. 发明授权

US09190323B2 Semiconductor devices with copper interconnects and methods for fabricating same 有权
标题翻译：具有铜互连的半导体器件及其制造方法
公开(公告)号：US09190323B2
公开(公告)日：2015-11-17
申请号：US13354070
申请日：2012-01-19
申请人： Xunyuan Zhang , Hoon Kim
发明人： Xunyuan Zhang , Hoon Kim
IPC分类号： H01L23/52 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76885 , H01L21/76838 , H01L21/76849 , H01L21/76852 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line.
摘要翻译：提供了具有铜互连的半导体器件及其制造方法。在一个实施例中，在诸如FEOL处理的衬底的衬底上用铜互连制造半导体器件。该方法包括在基板上形成铜层。铜层由晶粒形成。铜层被改性，使得改性铜层的平均粒度大于约0.05微米。在该方法中，蚀刻改性铜层以形成沿着衬底的线和从该线向上延伸的通孔。

8. 发明申请

US20130187273A1 SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND METHODS FOR FABRICATING SAME 有权
标题翻译：具有铜互连的半导体器件及其制造方法
公开(公告)号：US20130187273A1
公开(公告)日：2013-07-25
申请号：US13354070
申请日：2012-01-19
申请人： Xunyuan Zhang , Hoon Kim
发明人： Xunyuan Zhang , Hoon Kim
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76885 , H01L21/76838 , H01L21/76849 , H01L21/76852 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line.
摘要翻译：提供了具有铜互连的半导体器件及其制造方法。在一个实施例中，在诸如FEOL处理的衬底的衬底上用铜互连制造半导体器件。该方法包括在基板上形成铜层。铜层由晶粒形成。铜层被改性，使得改性铜层的平均粒度大于约0.05微米。在该方法中，蚀刻改性铜层以形成沿着衬底的线和从该线向上延伸的通孔。

9. 发明授权

US08431482B1 Integrated circuits and methods for processing integrated circuits with embedded features 有权
标题翻译：用于处理具有嵌入式功能的集成电路的集成电路和方法
公开(公告)号：US08431482B1
公开(公告)日：2013-04-30
申请号：US13362981
申请日：2012-01-31
申请人： Errol T. Ryan , Xunyuan Zhang
发明人： Errol T. Ryan , Xunyuan Zhang
IPC分类号： H01L21/4763
CPC分类号： H01L23/535 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L21/76886 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.
摘要翻译：提供集成电路，用于凹入衬底内的嵌入式铜特征的工艺，以及用于使集成电路的层间电介质衬底内的嵌入式铜互连凹陷的工艺。在一个实施例中，在诸如层间电介质基板的衬底内嵌入诸如嵌入式铜互连的嵌入式铜特征的方法包括提供其中布置有嵌入式铜特征的衬底。嵌入的铜特征具有暴露的表面，并且衬底具有与嵌入的铜特征的暴露表面相邻的衬底表面。嵌入的铜特征的暴露表面被氮化以在嵌入的铜特征中形成一层氮化铜。从嵌入的铜特征中选择性地蚀刻氮化铜以将嵌入的铜特征凹入到衬底内。

10. 发明申请

US20140024212A1 MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE 有权
标题翻译：用于互连结构的多层障碍层
公开(公告)号：US20140024212A1
公开(公告)日：2014-01-23
申请号：US13554020
申请日：2012-07-20
申请人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
发明人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
IPC分类号： H01L21/768
CPC分类号： H01L21/76873 , H01L21/76846 , H01L21/76858 , H01L21/76883 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.
摘要翻译：形成互连结构的方法包括在基板的电介质层中形成凹部。形成粘合阻挡层以使凹部成线。第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。在粘合阻挡层上方形成有应力降低阻挡层。所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。该凹部填充有填充层。

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