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    • 3. 发明授权
    • Multiple frequency phase-locked loop clock generator with stable
transitions between frequencies
    • 频率间稳定转换的多频锁相环时钟发生器
    • US5142247A
    • 1992-08-25
    • US741083
    • 1991-08-06
    • Henry F. Lada, Jr.Hung Q. LeJames H. GarrettJohn M. Gromala
    • Henry F. Lada, Jr.Hung Q. LeJames H. GarrettJohn M. Gromala
    • H03L7/18
    • H03L7/18
    • A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input of the PLL, with another frequency divider in the feedback loop of the PLL; each of these frequency dividers are selectable according to a signal on a select bus, translated by way of a ROM look-up table. The circuit also includes a multiplexer having a first input coupled to the PLL output, and a second input coupled to a stable clock signal, for example to the referenc clock signal or to the output of a fixed frequency PLL. The conrol input of the multiplexer is controlled by a state machine which monitors the select bus. Responsive to detection of a transition of the select bus, indicating a new frequency, the state machine issues a pulse to the control input of the multiplexer to cause it to select the stable clock signal for sufficient time to allow the PLL to acquire and lock onto the new frequency, after which the multiplexer again selects the PLL output as the output clock signal. As a result, the unstable and non-linear behavior at the PLL output does not appear at the output of the circuit, with a stable clock signal at a safe frequency appearing thereat during the PLL transitional cycles.
    • 锁相环(PLL)时钟发生器电路,其能够以稳定的方式改变其外部时钟信号的频率。 输出时钟信号的频率选择通过耦合在参考时钟信号和PLL的输入端之间的可选择的分压器与PLL的反馈环路中的另一个分频器进行; 这些分频器中的每一个可以根据选择总线上的信号进行选择,通过ROM查找表进行转换。 电路还包括具有耦合到PLL输出的第一输入和耦合到稳定时钟信号的第二输入的多路复用器,例如耦合到参考时钟信号或固定频率PLL的输出。 多路复用器的控制输入由监视选择总线的状态机控制。 响应于检测选择总线的转换,指示新的频率,状态机向多路复用器的控制输入端发出脉冲,使其选择稳定的时钟信号足够的时间以允许PLL获取并锁定到 新的频率,之后复用器再次选择PLL输出作为输出时钟信号。 因此,PLL输出端的不稳定和非线性特性不会出现在电路的输出端,稳定的时钟信号出现在PLL过渡周期内的安全频率。
    • 5. 发明授权
    • Handheld option pack identification scheme
    • 手持式选件包识别方案
    • US07039742B1
    • 2006-05-02
    • US09722890
    • 2000-11-27
    • Henry F. LadaJoseph A. Lightfoot
    • Henry F. LadaJoseph A. Lightfoot
    • G06F13/38G06F3/00
    • G06F1/3203G06F1/1626G06F1/1632G06F1/266G06F2200/1632G06F2200/1634
    • An insertion and identification scheme between the main unit of a Personal Digital Assistant (PDA) or handheld device and an option pack. Upon insertion, the hardware interface invokes a device manager on the main unit that interrogates the option pack on its features without significantly impacting battery life. The interrogation includes data on drivers, applications, configuration and miscellaneous requirements of the option pack. This identification process allows the option pack to store information, drivers and applications on the option pack, so the main unit does not have to use its memory to store information on a large number of option packs. Further, the insertion scheme provides a means of checking the power availability in the main unit before allowing the option pack to fully power-on.
    • 个人数字助理(PDA)或手持设备的主单元与选件包之间的插入和识别方案。 插入后,硬件接口调用主机上的设备管理器,在其功能上询问选件包,而不会显着影响电池寿命。 询问包括有关选件包的驱动程序,应用程序,配置和其他要求的数据。 此识别过程允许选件包在选件包上存储信息,驱动程序和应用程序,因此主机不必使用其内存来存储大量选件包上的信息。 此外,插入方案提供了在允许选项包完全通电之前检查主单元中的电力可用性的手段。