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1. 发明授权

US08586473B1 Methods for fabricating integrated circuits with ruthenium-lined copper 有权
标题翻译：用钌衬铜制造集成电路的方法
公开(公告)号：US08586473B1
公开(公告)日：2013-11-19
申请号：US13533816
申请日：2012-06-26
申请人： Kunaljeet Tanwar , Xunyuan Zhang , Ming He
发明人： Kunaljeet Tanwar , Xunyuan Zhang , Ming He
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a dielectric layer defining a plane. In the method, the dielectric layer is etched to form trenches. Then, a ruthenium-containing liner layer is deposited overlying the dielectric layer. The trenches are filled with copper-containing metal. The method includes recessing the copper-containing metal in each trench to form a space between the copper-containing metal and the plane. The space is filled with a capping layer. The layers are then planarized to at least the plane.
摘要翻译：提供了制造集成电路的方法。在一个实施例中，一种用于制造集成电路的方法包括沉积限定平面的电介质层。在该方法中，蚀刻介电层以形成沟槽。然后，沉积覆盖在介电层上的含钌衬里层。沟槽用含铜金属填充。该方法包括在每个沟槽中凹入含铜金属，以在含铜金属和平面之间形成空间。空间填充有覆盖层。然后将这些层平坦化至少至该平面。

2. 发明申请

US20140057435A1 METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：在集成电路设备上形成基于铜基导电结构的金属层的方法
公开(公告)号：US20140057435A1
公开(公告)日：2014-02-27
申请号：US13591341
申请日：2012-08-22
申请人： Xunyuan Zhang , Kunaljeet Tanwar , Ming He
发明人： Xunyuan Zhang , Kunaljeet Tanwar , Ming He
IPC分类号： H01L21/768
CPC分类号： H01L21/76849
摘要： Disclosed herein are various methods of forming a metal cap layer on copper-based conductive structures on integrated circuit devices, and integrated circuit devices having such a structure. In one example, the method includes the steps of forming a conductive feature comprised of copper in a layer of insulating material, performing a metal removal process to remove a portion of the conductive feature and thereby define a recess above a residual portion of the copper feature, and performing a selective deposition process to form a cap layer comprised of cobalt, manganese, CoWP or NiWP within the recess.
摘要翻译：本文公开了在集成电路器件上的铜基导电结构上形成金属覆盖层的各种方法，以及具有这种结构的集成电路器件。在一个示例中，该方法包括以下步骤：在绝缘材料层中形成由铜构成的导电特征，执行金属去除工艺以去除导电特征的一部分，从而在铜特征的残余部分上方限定凹陷并且进行选择性沉积工艺以在凹部内形成由钴，锰，CoWP或NiWP组成的覆盖层。

3. 发明授权

US08669176B1 BEOL integration scheme for copper CMP to prevent dendrite formation 有权
标题翻译： BEOL集成方案为铜CMP防止枝晶形成
公开(公告)号：US08669176B1
公开(公告)日：2014-03-11
申请号：US13596198
申请日：2012-08-28
申请人： Kunaljeet Tanwar
发明人： Kunaljeet Tanwar
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , H01L21/76832 , H01L21/76834
摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices by performing a copper deposition process to fill the trench or via with copper, which can be performed by fill, plating or electroless deposition. Copper clearing of copper overburden is performed using CMP to stop on an existing liner. Copper in the trenches or vias is recessed by controlled etch. An Nblok cap layer is deposited to cap the trenches or vias so that copper is not exposed to ILD. Nblok overburden and adjacent liner is then removed by CMP. Nblok cap layer is then deposited. The proposed approach is an alternative CMP integration scheme that will eliminate the exposure of copper to ILD during CMP, will prevent any dendrite formation, can be used for all metal layers in BEOL stack, and can be utilized for multiple layers, as necessary, whenever copper CMP is desired.
摘要翻译：本文公开了通过执行铜沉积工艺以用铜填充沟槽或通孔来形成集成电路器件上的铜基导电结构的各种方法，其可以通过填充，电镀或无电沉积进行。使用CMP对铜覆盖层进行铜清除，以停止现有衬管。沟槽或通孔中的铜通过受控蚀刻凹陷。沉积Nblok覆盖层以覆盖沟槽或通孔以使铜不暴露于ILD。然后通过CMP去除Nblok上覆层和相邻的衬里。然后沉积Nblok盖层。所提出的方法是一种替代的CMP集成方案，其将在CMP期间消除铜暴露于ILD，将防止任何枝晶形成，可用于BEOL堆叠中的所有金属层，并且可以根据需要用于多层需要铜CMP。

4. 发明申请

US20140065815A1 BEOL INTEGRATION SCHEME FOR COPPER CMP TO PREVENT DENDRITE FORMATION 有权
标题翻译：用于铜CMP的BEOL整合方案以防止形成DENDRITE
公开(公告)号：US20140065815A1
公开(公告)日：2014-03-06
申请号：US13596198
申请日：2012-08-28
申请人： Kunaljeet Tanwar
发明人： Kunaljeet Tanwar
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/76832 , H01L21/76834
摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices by performing a copper deposition process to fill the trench or via with copper, which can be performed by fill, plating or electroless deposition. Copper clearing of copper overburden is performed using CMP to stop on an existing liner. Copper in the trenches or vias is recessed by controlled etch. An Nblok cap layer is deposited to cap the trenches or vias so that copper is not exposed to ILD. Nblok overburden and adjacent liner is then removed by CMP. Nblok cap layer is then deposited. The proposed approach is an alternative CMP integration scheme that will eliminate the exposure of copper to ILD during CMP, will prevent any dendrite formation, can be used for all metal layers in BEOL stack, and can be utilized for multiple layers, as necessary, whenever copper CMP is desired.
摘要翻译：本文公开了通过执行铜沉积工艺以用铜填充沟槽或通孔来形成集成电路器件上的铜基导电结构的各种方法，其可以通过填充，电镀或无电沉积进行。使用CMP对铜覆盖层进行铜清除，以停止现有衬管。沟槽或通孔中的铜通过受控蚀刻凹陷。沉积Nblok覆盖层以覆盖沟槽或通孔以使铜不暴露于ILD。然后通过CMP去除Nblok上覆层和相邻的衬里。然后沉积Nblok盖层。所提出的方法是一种替代的CMP集成方案，其将在CMP期间消除铜暴露于ILD，将防止任何枝晶形成，可用于BEOL堆叠中的所有金属层，并且可以根据需要用于多层需要铜CMP。

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