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1. 发明申请

US20130075831A1 METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER 审中-公开
标题翻译：金属门盖有天然气阻塞/湿润层
公开(公告)号：US20130075831A1
公开(公告)日：2013-03-28
申请号：US13244355
申请日：2011-09-24
申请人： Shiu-Ko JangJian , Szu-An Wu , Ying-Lang Wang , Chi-Wen Liu
发明人： Shiu-Ko JangJian , Szu-An Wu , Ying-Lang Wang , Chi-Wen Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting/blocking layer.
摘要翻译：公开了具有TiAlN阻挡/润湿层的金属栅极堆叠及其制造方法。在一个示例中，集成电路器件包括设置在半导体衬底上的半导体衬底和栅极堆叠。栅极堆叠包括设置在半导体衬底上的栅介质层; 设置在所述栅极介电层上的功函数层; 设置在所述功函数层上的多功能润湿/阻挡层，其中所述多功能润湿/阻挡层是氮化铝钛层; 以及设置在多功能润湿/阻挡层上的导电层。

2. 发明授权

US06979656B2 Carbon and halogen doped silicate glass dielectric layer and method for fabricating the same 失效
标题翻译：碳和卤素掺杂的硅酸盐玻璃介电层及其制造方法
公开(公告)号：US06979656B2
公开(公告)日：2005-12-27
申请号：US10729217
申请日：2003-12-04
申请人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
发明人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
IPC分类号： H01L21/31 , H01L21/316 , H01L21/76 , H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , C23C16/401 , H01L21/02126 , H01L21/02131 , H01L21/02211 , H01L21/02274 , H01L21/31629 , H01L21/31633 , H01L21/76802 , H01L21/76807 , H01L21/76835 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.
摘要翻译：制造电介质层的方法提供了当形成碳和卤素掺杂的硅酸盐玻璃介电层时与卤素源材料分开的碳源材料的使用。当形成碳和卤素掺杂的硅酸盐玻璃介电层时，使用单独的碳和卤素源材料提供了增强的工艺自由度。具有大于约3.0的介电常数的这种碳和卤素掺杂的硅酸盐玻璃介电层特别适用于镶嵌法中的本征平面化停止层。包含碳和卤素掺杂的硅酸盐玻璃的双层电介质层结构和不含卤素掺杂的碳掺杂的硅酸盐玻璃介电层在双镶嵌方法中是有用的。

3. 发明申请

US20050121751A1 Carbon and halogen doped silicate glass dielectric layer and method for fabricating the same 失效
公开(公告)号：US20050121751A1
公开(公告)日：2005-06-09
申请号：US10729217
申请日：2003-12-04
申请人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
发明人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
IPC分类号： H01L21/31 , H01L21/316 , H01L21/76 , H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , C23C16/401 , H01L21/02126 , H01L21/02131 , H01L21/02211 , H01L21/02274 , H01L21/31629 , H01L21/31633 , H01L21/76802 , H01L21/76807 , H01L21/76835 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

4. 发明授权

US07071100B2 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US07071100B2
公开(公告)日：2006-07-04
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

5. 发明申请

US20050191855A1 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US20050191855A1
公开(公告)日：2005-09-01
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

6. 发明授权

US06903019B2 CMP process leaving no residual oxide layer or slurry particles 失效
标题翻译： CMP工艺不留下残留的氧化物层或浆料颗粒
公开(公告)号：US06903019B2
公开(公告)日：2005-06-07
申请号：US10706495
申请日：2003-11-12
申请人： Ying-Lang Wang , Shih-Chi Lin , Yi-Lung Cheng , Chi-Wen Liu , Ming-Hua Yoo , Wen-Kung Cheng , Jiann-Kwang Wang
发明人： Ying-Lang Wang , Shih-Chi Lin , Yi-Lung Cheng , Chi-Wen Liu , Ming-Hua Yoo , Wen-Kung Cheng , Jiann-Kwang Wang
IPC分类号： C09G1/02 , H01L21/321 , H01L21/768 , H01L21/461
CPC分类号： C09G1/02 , H01L21/3212 , H01L21/7684
摘要： Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.
摘要翻译：当前执行的CMP中看到的两个问题是浆料颗粒保留在表面上并形成最后一层氧化物的倾向。这些问题已经通过向浆料中加入一定量的TMAH或TBAH来解决。这具有使表面被抛光的疏水性的效果。在该状态下，在CMP结束时，残留的氧化层不会残留在表面上。许多浆料磨料颗粒也不会保持粘附到新鲜抛光的表面。那些可以通过简单的冲洗或抛光容易地去除。作为替代方案，CMP工艺可以在三个阶段进行 - 第一个惯例CMP，然后在TMAH或TBAH的溶液中抛光，最后进行温和的冲洗或抛光。

7. 发明申请

US20050056544A1 Dual contact ring and method for metal ECP process 有权
标题翻译：双接触环和金属ECP工艺方法
公开(公告)号：US20050056544A1
公开(公告)日：2005-03-17
申请号：US10664347
申请日：2003-09-16
申请人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
IPC分类号： C25D5/02 , C25D5/48 , B23H7/26
CPC分类号： C25D5/48 , C25D5/028 , Y10S204/07
摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.
摘要翻译：用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。外部电压环连接到正电压源，内部电压环连接到负电压源。内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

8. 发明授权

US07125802B2 CMP process leaving no residual oxide layer or slurry particles 有权
公开(公告)号：US07125802B2
公开(公告)日：2006-10-24
申请号：US10696432
申请日：2003-10-29
申请人： Ying-Lang Wang , Shih-Chi Lin , Yi-Lung Cheng , Chi-Wen Liu , Ming-Hua Yoo , Wen-Kung Cheng , Jiann-Kwang Wang
发明人： Ying-Lang Wang , Shih-Chi Lin , Yi-Lung Cheng , Chi-Wen Liu , Ming-Hua Yoo , Wen-Kung Cheng , Jiann-Kwang Wang
IPC分类号： H01L21/306
CPC分类号： C09G1/02 , H01L21/3212 , H01L21/7684
摘要： Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

9. 发明申请

US20050275941A1 Metal-filled openings for submicron devices and methods of manufacture thereof 有权
标题翻译：用于亚微米器件的金属填充开口及其制造方法
公开(公告)号：US20050275941A1
公开(公告)日：2005-12-15
申请号：US10854061
申请日：2004-05-26
申请人： Chi-Wen Liu , Jung-Chih Tsao , Shih-Tzung Chang , Ying-Lang Wang , Kei-Wei Chen
发明人： Chi-Wen Liu , Jung-Chih Tsao , Shih-Tzung Chang , Ying-Lang Wang , Kei-Wei Chen
IPC分类号： G02B23/00 , H01L21/768 , H01L21/82
CPC分类号： H01L21/7684 , H01L21/76877
摘要： A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.
摘要翻译：在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层，其中导电体层具有第一晶粒尺寸。导电盖层形成在导电体层之上，导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。

10. 发明授权

US07252750B2 Dual contact ring and method for metal ECP process 有权
标题翻译：双接触环和金属ECP工艺方法
公开(公告)号：US07252750B2
公开(公告)日：2007-08-07
申请号：US10664347
申请日：2003-09-16
申请人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
IPC分类号： C25D17/00
CPC分类号： C25D5/48 , C25D5/028 , Y10S204/07
摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.
摘要翻译：用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。外部电压环连接到正电压源，内部电压环连接到负电压源。内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

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