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1. 发明申请

US20140016414A1 FLASH MEMORY 有权
标题翻译：闪存
公开(公告)号：US20140016414A1
公开(公告)日：2014-01-16
申请号：US13546036
申请日：2012-07-11
申请人： Yu-Hsiung Tsai , Yuan-Tai Lin , Ching-Yuan Lin , Chao-Wei Kuo , Shang-Wei Fang , Wein-Town Sun
发明人： Yu-Hsiung Tsai , Yuan-Tai Lin , Ching-Yuan Lin , Chao-Wei Kuo , Shang-Wei Fang , Wein-Town Sun
IPC分类号： G11C16/04
CPC分类号： G11C13/0069 , G11C13/0064 , G11C16/04 , G11C16/12
摘要： The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
摘要翻译：本发明提供一种包括存储单元，限流器和编程电压发生器的闪速存储器。响应于编程电流和编程电压对存储单元进行编程。电流限制器通过数据线信号（例如数据线电压）反映节目电流的量。程序电压发生器响应于数据线电压产生并控制编程电压，使得编程电流可以跟踪恒定的参考电流。

2. 发明授权

US08817543B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US08817543B2
公开(公告)日：2014-08-26
申请号：US13546036
申请日：2012-07-11
申请人： Yu-Hsiung Tsai , Yuan-Tai Lin , Ching-Yuan Lin , Chao-Wei Kuo , Shang-Wei Fang , Wein-Town Sun
发明人： Yu-Hsiung Tsai , Yuan-Tai Lin , Ching-Yuan Lin , Chao-Wei Kuo , Shang-Wei Fang , Wein-Town Sun
IPC分类号： G11C11/34 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C16/04 , G11C16/12
摘要： The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
摘要翻译：本发明提供一种包括存储单元，限流器和编程电压发生器的闪速存储器。响应于编程电流和编程电压对存储单元进行编程。电流限制器通过数据线信号（例如数据线电压）反映节目电流的量。程序电压发生器响应于数据线电压产生并控制编程电压，使得编程电流可以跟踪恒定的参考电流。

3. 发明申请

US20080080249A1 NON-VOLATILE MEMORY, FABRICATING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非挥发性记忆，制作方法及其操作方法
公开(公告)号：US20080080249A1
公开(公告)日：2008-04-03
申请号：US11762084
申请日：2007-06-13
申请人： Shi-Hsien Chen , Chao-Wei Kuo , Saysamone Pittikoun , Michael Yingli Liu
发明人： Shi-Hsien Chen , Chao-Wei Kuo , Saysamone Pittikoun , Michael Yingli Liu
IPC分类号： G11C11/34 , H01L29/792
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/42352 , H01L29/7926
摘要： A non-volatile memory having a memory cell formed on a substrate is provided. A trench is formed in the substrate. The memory cell has a first gate, a second gate, a charge storage layer, a first source/drain region and a second source/drain region. The first gate is disposed in the trench of the substrate. The second gate is disposed on the substrate at one side of the trench. The charge storage layer is disposed between the first gate and the substrate and between the second gate and the substrate. The first source/drain region is disposed in the substrate at the bottom of the trench. The second source/drain region is disposed in the substrate at one side of the second gate.
摘要翻译：提供了具有形成在基板上的存储单元的非易失性存储器。在衬底中形成沟槽。存储单元具有第一栅极，第二栅极，电荷存储层，第一源极/漏极区域以及第二源极/漏极区域。第一栅极设置在衬底的沟槽中。第二栅极设置在沟槽一侧的衬底上。电荷存储层设置在第一栅极和衬底之间以及第二栅极和衬底之间。第一源极/漏极区域设置在沟槽底部的衬底中。第二源极/漏极区域设置在第二栅极的一侧的衬底中。

4. 发明申请

US20070206424A1 METHOD FOR ERASING NON-VOLATILE MEMORY 审中-公开
标题翻译：用于擦除非易失性存储器的方法
公开(公告)号：US20070206424A1
公开(公告)日：2007-09-06
申请号：US11531690
申请日：2006-09-13
申请人： Chao-Wei Kuo , Chih-Ming Chao , Hann-Ping Hwang
发明人： Chao-Wei Kuo , Chih-Ming Chao , Hann-Ping Hwang
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/14
摘要： A method for erasing a non-volatile memory is provided. The non-volatile memory includes a first conductive type substrate, a second conductive type well disposed in the first conductive type substrate, a first conductive type well disposed on the second conductive type well, and a memory cell disposed on the first conductive type substrate. The memory cell includes a charge trapping layer and a gate. The erasing method includes the following steps. A first voltage is applied to the gate, a second voltage is applied to the first conductive type substrate, and the second conductive type well is floating. The second voltage is large enough to induce a substrate hot hole effect. The holes are injected into the charge trapping layer by applying the first voltage.
摘要翻译：提供了一种擦除非易失性存储器的方法。非易失性存储器包括第一导电型衬底，布置在第一导电类型衬底中的第二导电类型阱，布置在第二导电类型阱上的第一导电类型阱以及设置在第一导电类型衬底上的存储单元。存储单元包括电荷捕获层和栅极。擦除方法包括以下步骤。向栅极施加第一电压，将第二电压施加到第一导电型衬底，并且第二导电类型阱浮置。第二电压足够大以引起基板热孔效应。通过施加第一电压将空穴注入电荷俘获层。

5. 发明申请

US20060216893A1 MANUFACTURING METHOD OF A FLASH MEMORY CELL 审中-公开
标题翻译：闪存存储器的制造方法
公开(公告)号：US20060216893A1
公开(公告)日：2006-09-28
申请号：US11308806
申请日：2006-05-09
申请人： Leo Wang , Chien-Chih Du , Chao-Wei Kuo , Cheng-Tung Huang , Saysamone Pittikoun
发明人： Leo Wang , Chien-Chih Du , Chao-Wei Kuo , Cheng-Tung Huang , Saysamone Pittikoun
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： H01L27/11521 , H01L27/115
摘要： A manufacturing method of a flash memory cell is provided. The flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide layer is disposed within the first conductive type drain region. The contact plug is disposed within the inter-layer dielectric layer and electrically connected with the metal silicide layer in the first conductive type drain region to reduce resistance between the contact plug, the first conductive type drain region and the second conductive type shallow well and increase read-out speed of the flash memory.
摘要翻译：提供了闪存单元的制造方法。闪存单元包括第一导电类型衬底，堆叠栅极结构，第一导电类型源极/漏极区域，金属硅化物层，层间电介质层和接触插塞。第一导电型衬底具有已经形成在其上的第二导电型浅阱。金属硅化物层设置在第一导电类型漏极区域内。接触插塞设置在层间电介质层内并与第一导电类型漏极区域中的金属硅化物层电连接，以减小接触插塞，第一导电类型漏极区域和第二导电类型浅阱之间的电阻，并增加闪存的读出速度。

6. 发明申请

US20050280068A1 FLASH MEMORY CELL AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：闪存存储单元及其制造方法
公开(公告)号：US20050280068A1
公开(公告)日：2005-12-22
申请号：US10908577
申请日：2005-05-18
申请人： Leo Wang , Chien-Chih Du , Chao-Wei Kuo , Cheng-Tung Huang , Saysamone Pittikoun
发明人： Leo Wang , Chien-Chih Du , Chao-Wei Kuo , Cheng-Tung Huang , Saysamone Pittikoun
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/732
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide layer is disposed within the first conductive type drain region. The contact plug is disposed within the inter-layer dielectric layer and electrically connected with the metal silicide layer in the first conductive type drain region to reduce resistance between the contact plug, the first conductive type drain region and the second conductive type shallow well and increase read-out speed of the flash memory.
摘要翻译：闪存单元包括第一导电类型衬底，堆叠栅极结构，第一导电类型源极/漏极区域，金属硅化物层，层间电介质层和接触插塞。第一导电型衬底具有已经形成在其上的第二导电型浅阱。金属硅化物层设置在第一导电类型漏极区域内。接触插塞设置在层间电介质层内并与第一导电类型漏极区域中的金属硅化物层电连接，以减小接触插塞，第一导电类型漏极区域和第二导电类型浅阱之间的电阻，并增加闪存的读出速度。

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