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1. 发明授权

US08822319B2 Method of manufacturing non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US08822319B2
公开(公告)日：2014-09-02
申请号：US13610875
申请日：2012-09-12
申请人： Cheng-Yen Shen , Wein-Town Sun
发明人： Cheng-Yen Shen , Wein-Town Sun
IPC分类号： H01L21/28
CPC分类号： H01L27/11573 , H01L21/28273 , H01L21/823456 , H01L21/823462 , H01L21/82385 , H01L21/823857 , H01L27/11529 , H01L27/11546
摘要： A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.
摘要翻译：提供一种制造非易失性存储器的方法。衬底包括存储单元区域和第一外围电路区域。存储单元区域包括选择晶体管区域。在第一外围电路区域和选择晶体管区域的基板上形成具有第一厚度的第一栅极介质层。去除选择晶体管区域上的第一栅极电介质层的一部分以形成第二栅极介电层。第二介电层具有第二厚度，其中第二厚度小于第一厚度。

2. 发明申请

US20130064027A1 Memory and Method of Adjusting Operating Voltage thereof 审中-公开
标题翻译：记忆和调整其工作电压的方法
公开(公告)号：US20130064027A1
公开(公告)日：2013-03-14
申请号：US13231980
申请日：2011-09-14
申请人： Meng-Yi Wu , Wein-Town Sun , Yen-Tai Lin , Cheng-Jye Liu , Chiun-Chi Shen
发明人： Meng-Yi Wu , Wein-Town Sun , Yen-Tai Lin , Cheng-Jye Liu , Chiun-Chi Shen
IPC分类号： G11C29/00
CPC分类号： G11C29/021 , G11C11/40 , G11C29/028 , G11C29/50016 , G11C2029/5002
摘要： By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.
摘要翻译：通过根据指示存储单元的未测试电容器的电容的测量电容结果来调节存储器中的存储单元的工作电压，可以总是根据所测量的电容结果确定存储单元的适当工作电压。测量的电容结果表示指示存储单元的栅极电介质的特性的未测试电容器的电容是否高于或低于参考电容器，并且通过放大表示参考电容器的电容的两个电压之间的差来产生和被测电容器的电容。

3. 发明授权

US08369154B2 Channel hot electron injection programming method and related device 有权
标题翻译：通道热电子注入编程方法及相关器件
公开(公告)号：US08369154B2
公开(公告)日：2013-02-05
申请号：US12944711
申请日：2010-11-11
申请人： Ying-Je Chen , Yun-Jen Ting , Wein-Town Sun , Kai-Yuan Hsiao , Cheng-Jye Liu
发明人： Ying-Je Chen , Yun-Jen Ting , Wein-Town Sun , Kai-Yuan Hsiao , Cheng-Jye Liu
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/3468
摘要： A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.
摘要翻译：用于减少编程电流和提高可靠性的非易失性存储器件包括存储单元阵列，写入电路和验证电路。存储单元阵列包括布置在存储单元阵列的位线和字线矩阵的交叉点处的存储单元。写电路为每个字线提供多个可变脉冲进行编程。多个可变脉冲具有预定的幅度，以在编程操作期间降低导通电流，保持栅极注入电流大致最大。验证电路在编程操作期间感测导通电流的变化，并且如果在编程操作期间感测到的传导电流达到预定值，则禁止编程操作。

4. 发明授权

US08115209B2 Dual gate layout for thin film transistor 有权
标题翻译：薄膜晶体管的双栅极布局
公开(公告)号：US08115209B2
公开(公告)日：2012-02-14
申请号：US13026453
申请日：2011-02-14
申请人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
发明人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
IPC分类号： H01L29/04 , H01L29/15 , H01L31/036 , H01L29/10 , H01L31/0376 , H01L31/20 , H01L29/76 , H01L31/112 , H01L27/108 , H01L29/12 , H01L31/062 , H01L31/113 , H01L31/00
CPC分类号： H01L29/78645 , H01L27/12 , H01L29/42384 , H01L29/78621
摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.
摘要翻译：公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。该布局包括：（1）具有从顶部形成的L形或蛇形的衬底上的多晶硅，其具有重掺杂源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区域，第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。栅极金属与多晶硅层相交，限定了前述栅极沟道。在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

5. 发明授权

US07915117B2 Method for forming a pixel of an electroluminescence device having storage capacitors 有权
标题翻译：用于形成具有存储电容器的电致发光器件的像素的方法
公开(公告)号：US07915117B2
公开(公告)日：2011-03-29
申请号：US11616943
申请日：2006-12-28
申请人： Wein-Town Sun
发明人： Wein-Town Sun
IPC分类号： H01L21/8242
CPC分类号： H01L27/3265 , H01L27/12 , H01L27/13
摘要： An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.
摘要翻译：电致发光（EL）器件包括衬底和形成在衬底上的多个像素。每个像素包括至少包括第一电容器和第二电容器的第一区域，第一电容器包括第一导电层，第一导电层上的第一电介质层和第一介电层上的第二导电层，包括第二导电层的电容器，在第二导电层上的第二电介质层，以及在第二介电层上的第三导电层，以及包括形成在衬底上的第一半导体层的第二区域，半导体层和第一栅极氧化物层上的第四导电层。

6. 发明申请

US20110069099A1 CURRENT-DRIVEN OLED PANEL AND RELATED PIXEL STRUCTURE 有权
标题翻译：电流驱动OLED面板和相关像素结构
公开(公告)号：US20110069099A1
公开(公告)日：2011-03-24
申请号：US12957398
申请日：2010-12-01
申请人： Wein-Town Sun
发明人： Wein-Town Sun
IPC分类号： G09G5/02 , G09G3/32
CPC分类号： G09G3/3241 , G09G2300/0842
摘要： A pixel structure includes a light-emitting device (LED); a first scan line; a data line; a first transistor having a gate coupled to the first scan line; and a current mirror electrically connected to the LED. The current mirror includes a second transistor having a gate connected to the data line and one of the source and the drain of the first transistor, and one of a source and a drain coupled to a first voltage source; and a third transistor having a gate coupled to the other of the source and the drain of the first transistor, one of a source and a drain coupled the first voltage source. The LED is coupled between the other of the source and the drain of the third transistor and a second voltage source whose voltage level is greater than a voltage level of the first voltage source.
摘要翻译：像素结构包括发光器件（LED）; 第一条扫描线; 数据线第一晶体管，具有耦合到第一扫描线的栅极; 以及与LED连接的电流镜。电流镜包括第二晶体管，其具有连接到数据线的栅极，以及第一晶体管的源极和漏极中的一个以及耦合到第一电压源的源极和漏极之一; 以及第三晶体管，其具有耦合到第一晶体管的源极和漏极中的另一个的栅极，源极和漏极中的一个耦合第一电压源。 LED耦合在第三晶体管的源极和漏极中的另一个和第二电压源之间，其电压电平大于第一电压源的电压电平。

7. 发明授权

US07910933B2 Dual gate layout for thin film transistor 有权
标题翻译：薄膜晶体管的双栅极布局
公开(公告)号：US07910933B2
公开(公告)日：2011-03-22
申请号：US12469298
申请日：2009-05-20
申请人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
发明人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
IPC分类号： H01L29/04 , H01L29/15 , H01L31/036 , H01L29/10 , H01L31/0376 , H01L31/20 , H01L29/76 , H01L31/112 , H01L27/108 , H01L29/12 , H01L31/062 , H01L31/113 , H01L31/00
CPC分类号： H01L29/78645 , H01L27/12 , H01L29/42384 , H01L29/78621
摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.
摘要翻译：公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。该布局包括：（1）具有从顶部形成的L形或蛇形的衬底上的多晶硅，其具有重掺杂源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区域，第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。栅极金属与多晶硅层相交，限定了前述栅极沟道。在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

8. 发明授权

US07696966B2 Liquid crystal display and driving method therefor 有权
标题翻译：液晶显示及其驱动方法
公开(公告)号：US07696966B2
公开(公告)日：2010-04-13
申请号：US11456871
申请日：2006-07-12
申请人： Wein-Town Sun , Chien-Chih Chen
发明人： Wein-Town Sun , Chien-Chih Chen
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3607 , G09G3/3614 , G09G2310/0297 , G09G2320/0214 , G09G2320/0233
摘要： A liquid crystal display and its driving method are disclosed. Among the pixels driven by the same data driving unit, firstly the pixels of same color are sequentially driven, and then the pixels of other colors are sequentially driven, so that the pixels have almost the same leakage current.
摘要翻译：公开了一种液晶显示器及其驱动方法。在由相同数据驱动单元驱动的像素中，首先依次驱动相同颜色的像素，然后依次驱动其他颜色的像素，使得像素具有几乎相同的漏电流。

9. 发明授权

US07598795B2 Negative voltage converter 有权
标题翻译：负电压转换器
公开(公告)号：US07598795B2
公开(公告)日：2009-10-06
申请号：US11833889
申请日：2007-08-03
申请人： Kung-hong Lee , Cheng-chiu Pai , Shi-hsiang Lu , Wein-town Sun
发明人： Kung-hong Lee , Cheng-chiu Pai , Shi-hsiang Lu , Wein-town Sun
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/071
摘要： A negative voltage converter includes six transistors. A first end and a control end of a first transistor are coupled to a signal input. A first end of a second transistor is coupled to the signal input, and a control end of which is coupled to a first clock and the first transistor. A first end of a third transistor is coupled to the signal input, a control end of the third transistor is coupled with a second clock and the second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a control end of which is coupled with the first clock and the third transistor. A first end of a fifth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the second clock and the fourth transistor A first end of a sixth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the first clock and the fifth transistor.
摘要翻译：负电压转换器包括六个晶体管。第一晶体管的第一端和控制端耦合到信号输入端。第二晶体管的第一端耦合到信号输入，其控制端耦合到第一时钟和第一晶体管。第三晶体管的第一端耦合到信号输入，第三晶体管的控制端与第二时钟和第二晶体管耦合。第四晶体管的第一端耦合到第三晶体管的第二端，其控制端与第一时钟和第三晶体管耦合。第五晶体管的第一端耦合到第三晶体管的第二端，并且其控制端与第二时钟耦合，第四晶体管A第六晶体管的第一端耦合到第三晶体管的第二端晶体管，其控制端与第一时钟和第五晶体管耦合。

10. 发明授权

US07586121B2 Electroluminescence device having stacked capacitors 有权
标题翻译：具有堆叠电容器的电致发光器件
公开(公告)号：US07586121B2
公开(公告)日：2009-09-08
申请号：US11005648
申请日：2004-12-07
申请人： Wein-Town Sun
发明人： Wein-Town Sun
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L27/3265 , H01L27/12 , H01L27/13
摘要： An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.
摘要翻译：电致发光（EL）器件包括衬底和形成在衬底上的多个像素。每个像素包括至少包括第一电容器和第二电容器的第一区域，第一电容器包括第一导电层，第一导电层上的第一电介质层和第一介电层上的第二导电层，包括第二导电层的电容器，在第二导电层上的第二电介质层，以及在第二介电层上的第三导电层，以及包括形成在衬底上的第一半导体层的第二区域，半导体层和第一栅极氧化物层上的第四导电层。

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