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1. 发明申请

US20120061785A1 SEMICONDUCTOR LIGHT DETECTING ELEMENT AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体光检测元件及其制造方法
公开(公告)号：US20120061785A1
公开(公告)日：2012-03-15
申请号：US13320912
申请日：2010-06-02
申请人： Yoshitaka Ishikawa , Akira Sakamoto , Kazuhisa Yamamura , Satoshi Kawai
发明人： Yoshitaka Ishikawa , Akira Sakamoto , Kazuhisa Yamamura , Satoshi Kawai
IPC分类号： H01L31/0236
CPC分类号： H01L31/02363 , H01L31/0232 , H01L31/103 , H01L31/109 , Y02E10/50
摘要： A photodiode PD1 is provided with an n− type semiconductor substrate 1 with a pn junction formed of a first conductivity type semiconductor region and a second conductivity type semiconductor region. For the n− type semiconductor substrate 1, an accumulation layer 7 is formed on the second principal surface 1b side of the n− type semiconductor substrate 1 and an irregular asperity 10 is formed at least in regions opposed to the pn junction in a first principal surface 1a and in the second principal surface 1b. The regions opposed to the pn junction in the first principal surface 1a and in the second principal surface 1b of the n− type semiconductor substrate 1 are optically exposed.
摘要翻译：光电二极管PD1设置有具有由第一导电类型半导体区域和第二导电类型半导体区域形成的pn结的n型半导体衬底1。对于n型半导体衬底1，在n型半导体衬底1的第二主表面1b侧上形成有积累层7，并且至少在第一主体中与pn结相对的区域中形成不规则凹凸10 表面1a和第二主表面1b中。在n型半导体衬底1的第一主表面1a和第二主表面1b中与pn结相对的区域被光学曝光。

2. 发明申请

US20110291218A1 PHOTODIODE AND PHOTODIODE ARRAY 有权
标题翻译：光电和光电子阵列
公开(公告)号：US20110291218A1
公开(公告)日：2011-12-01
申请号：US13147884
申请日：2010-02-15
申请人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yoshitaka Ishikawa , Satoshi Kawai
发明人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yoshitaka Ishikawa , Satoshi Kawai
IPC分类号： H01L27/146 , H01L31/09
CPC分类号： H01L27/1464 , H01L27/1462 , H01L27/14625 , H01L27/1463 , H01L27/14649 , H01L27/14689 , H01L31/0232 , H01L31/0236 , H01L31/02363 , H01L31/035281 , H01L31/103 , H01L31/107 , H01L2224/48091 , Y02E10/50 , H01L2924/00014
摘要： A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p− type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CR The p− type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.
摘要翻译：光电二极管阵列PDA1设置有基板S，其中多个受光通道CH具有n型半导体层32.光电二极管阵列PDA1设置有形成在n型半导体层32上的p型半导体层33，电阻设置在相应的光检测通道CH上，并且每个具有连接到信号导线23的一个端部，以及形成在多个光电通道CR之间的n型分离部分40. p型半导体层33形成在p型结与n型半导体层32接口，并且具有多个乘法区域AM，用于与检测目标光入射产生的载流子的雪崩乘法相对应的各个受光通道。在n型半导体层32的表面上形成不规则的凹凸10，并且该表面被光学曝光。

3. 发明授权

US09190551B2 Photodiode and photodiode array 有权
标题翻译：光电二极管和光电二极管阵列
公开(公告)号：US09190551B2
公开(公告)日：2015-11-17
申请号：US13202244
申请日：2010-02-15
申请人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yoshitaka Ishikawa , Satoshi Kawai
发明人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yoshitaka Ishikawa , Satoshi Kawai
IPC分类号： H01L33/22 , H01L31/107 , H01L27/144 , H01L31/0236 , H01L31/18 , H01L27/146
CPC分类号： H01L31/02366 , H01L27/1446 , H01L27/1464 , H01L31/0236 , H01L31/02363 , H01L31/028 , H01L31/107 , H01L31/1804 , Y02E10/547
摘要： A p− type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p− type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p− type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p− type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
摘要翻译： p型半导体衬底20具有彼此相对并包括感光区域21的第一主表面20a和第二主表面20b。感光区域21由n +型杂质区域23，p +型杂质区域25 以及在p型半导体衬底20中施加偏置电压而被耗尽的区域。在p型半导体衬底20的第二主表面20b中形成不规则的凹凸10.在 p型半导体衬底20的第二主表面20b侧和与感光区域21相对的累积层37中的区域被光学曝光。

4. 发明授权

US08742528B2 Photodiode and photodiode array 有权
标题翻译：光电二极管和光电二极管阵列
公开(公告)号：US08742528B2
公开(公告)日：2014-06-03
申请号：US13147884
申请日：2010-02-15
申请人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yoshitaka Ishikawa , Satoshi Kawai
发明人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yoshitaka Ishikawa , Satoshi Kawai
IPC分类号： H01L31/0232 , H01L27/146
CPC分类号： H01L27/1464 , H01L27/1462 , H01L27/14625 , H01L27/1463 , H01L27/14649 , H01L27/14689 , H01L31/0232 , H01L31/0236 , H01L31/02363 , H01L31/035281 , H01L31/103 , H01L31/107 , H01L2224/48091 , Y02E10/50 , H01L2924/00014
摘要： A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p− type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p− type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.
摘要翻译：光电二极管阵列PDA1设置有基板S，其中多个受光通道CH具有n型半导体层32.光电二极管阵列PDA1设置有形成在n型半导体层32上的p型半导体层33，电阻设置在相应的光检测通道CH上，每个具有连接到信号导线23的一个端部，以及形成在多个光电检测通道CH之间的n型分离部分40。 p型半导体层33在与n型半导体层32的界面处形成pn结，并且具有多个乘法区域AM，用于对应于各个受光通道而与检测目标光入射产生的载流子的雪崩乘法。在n型半导体层32的表面上形成不规则的凹凸10，并且该表面被光学曝光。

5. 发明申请

US20110298076A1 PHOTODIODE AND PHOTODIODE ARRAY 有权
标题翻译：光电和光电子阵列
公开(公告)号：US20110298076A1
公开(公告)日：2011-12-08
申请号：US13202244
申请日：2010-02-15
申请人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yoshitaka Ishikawa , Satoshi Kawai
发明人： Kazuhisa Yamamura , Akira Sakamoto , Terumasa Nagano , Yoshitaka Ishikawa , Satoshi Kawai
IPC分类号： H01L31/0236
CPC分类号： H01L31/02366 , H01L27/1446 , H01L27/1464 , H01L31/0236 , H01L31/02363 , H01L31/028 , H01L31/107 , H01L31/1804 , Y02E10/547
摘要： A p− type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p− type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p− type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p− type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
摘要翻译： p型半导体衬底20具有彼此相对并包括感光区域21的第一主表面20a和第二主表面20b。感光区域21由n +型杂质区域23，p +型杂质区域25 以及在p型半导体衬底20中施加偏置电压而被耗尽的区域。在p型半导体衬底20的第二主表面20b中形成不规则的凹凸10.在 p型半导体衬底20的第二主表面20b侧和与感光区域21相对的累积层37中的区域被光学曝光。

6. 发明授权

US5843204A Method for recycling iron and steel industry waste 失效
标题翻译：回收钢铁工业废弃物的方法
公开(公告)号：US5843204A
公开(公告)日：1998-12-01
申请号：US761989
申请日：1996-12-11
申请人： Yoshitaka Ishikawa , Susumu Ide , Toshio Matsuoka , Shinichi Kurozu , Hiroshi Koide , Shigeru Morishita , Tateki Mori
发明人： Yoshitaka Ishikawa , Susumu Ide , Toshio Matsuoka , Shinichi Kurozu , Hiroshi Koide , Shigeru Morishita , Tateki Mori
IPC分类号： F23G5/00 , C22B7/02 , F23G5/20 , F23G7/04 , F23J1/00 , F27B7/02 , F27B7/20 , F27B7/33 , C21B11/06
CPC分类号： F27B7/02 , C22B7/02 , F27B7/2083 , F27B2007/022 , Y02P10/216 , Y10S75/961
摘要： In a method of recycling iron and steel industry waste by processing the waste as an object substance by the use of a rotary kiln, the object substance is changed into a valuable material while the object substance travels within the rotary kiln from an upstream side to a downstream side. The object substance is heated on the upstream side of the rotary kiln within a reducing atmosphere to be reduced and molten into a reduced and molten product. The reduced and molten product is quickly sent to the downstream side without being adhered to an internal wall of the rotary kiln. The valuable material is extracted from the reduced and molten product which may be directly discharged out of the rotary kiln or which may be discharged after the reduced and molten product is once kept in a basin formed in the vicinity of the downstream side of the rotary kiln.
摘要翻译：在通过使用回转窑处理作为物体的废物来回收钢铁工业废弃物的方法中，将物体变成有价值的材料，同时物体在回转窑内从上游侧行进到下游侧。目标物质在还原气氛中在回转窑的上游侧被加热以被还原并熔化成还原和熔融的产物。还原和熔化的产品被快速地送到下游侧，而不粘附在回转窑的内壁上。从可以直接排出回转窑的还原熔融产物中提取有价值的材料，或者在还原熔融产物一次保存在形成于回转窑下游侧附近的盆中之后排出。

7. 发明授权

US3943583A Bed with a commode 失效
标题翻译：带一个小厨房的床
公开(公告)号：US3943583A
公开(公告)日：1976-03-16
申请号：US527279
申请日：1974-11-26
申请人： Yoshitaka Ishikawa
发明人： Yoshitaka Ishikawa
IPC分类号： A61G7/02
CPC分类号： A61G7/02
摘要： A bed provided with a commode or stool has a main mattress provided with a through-hole into which the commode or an auxiliary mattress may be positioned alternately by manipulation of an operating panel mounted at or near the bed. The front part of the main mattress may be erected along a transverse fold line so as to serve as reclining portion.
摘要翻译：设置有粪便或粪便的床具有设置有通孔的主床垫，通过操纵安装在床上或床附近的操作面板，可以交替地定位接口或辅助床垫。主床垫的前部可以沿横向折线竖起，以作为斜倚部分。

8. 发明申请

US20090121306A1 Photodiode Array 审中-公开
标题翻译：光电二极管阵列
公开(公告)号：US20090121306A1
公开(公告)日：2009-05-14
申请号：US11793651
申请日：2005-12-21
申请人： Yoshitaka Ishikawa
发明人： Yoshitaka Ishikawa
IPC分类号： H01L31/09
CPC分类号： H01L27/14663 , H01L27/1446 , H01L27/1463 , H01L31/107
摘要： The present invention provides a photodiode array which can secure a sufficient aperture ratio with respect to light to be detected while restraining crosstalk between photodetecting channels even during operation in Geiger mode. In a photodiode array 1, resistors 42 and wirings 43 to be electrically connected to avalanche multipliers 6, respectively, are collectively formed on the upper surface side of a semiconductor substrate 2. Therefore, by setting the lower surface side of the semiconductor substrate 2 as a light-incident side, a sufficient aperture ratio can be secured while restraining crosstalk between photodetecting channels 10 by separators 5. Furthermore, on the lower surface side of the semiconductor substrate 2, accumulation layers 7 are formed, so that high quantum efficiency in each photodetecting channel 10 is secured and the effective aperture ratio is improved. The accumulation layers 7 lower the contact resistance between the semiconductor substrate 2 and the transparent electrode layer 3 and make it possible to form a satisfactory contact.
摘要翻译：本发明提供一种光电二极管阵列，即使在盖革模式下操作时，也能够在抑制光检测通道之间的串扰的同时，确保相对于被检测光的足够的开口率。在光电二极管阵列1中，分别与半导体衬底2的上表面侧电连接到雪崩倍增器6的电阻器42和布线43共同形成。因此，通过将半导体衬底2的下表面侧设置为光入射侧，通过隔膜5抑制光检测通道10之间的串扰，可以确保充分的开口率。此外，在半导体基板2的下表面侧形成有积累层7，从而在每个光电检测通道10被固定，有效开口率得到改善。累积层7降低半导体衬底2和透明电极层3之间的接触电阻，并且可以形成令人满意的接触。

9. 发明授权

US5654536A Photomultiplier having a multilayer semiconductor device 失效
标题翻译：具有多层半导体器件的光电倍增管
公开(公告)号：US5654536A
公开(公告)日：1997-08-05
申请号：US557541
申请日：1995-11-14
申请人： Motohiro Suyama , Masaharu Muramatsu , Makoto Oishi , Yoshitaka Ishikawa , Koei Yamamoto
发明人： Motohiro Suyama , Masaharu Muramatsu , Makoto Oishi , Yoshitaka Ishikawa , Koei Yamamoto
IPC分类号： H01J43/04 , H01J43/12 , H01L31/107 , H01J40/14
CPC分类号： H01L31/1075 , H01J43/04 , H01J43/12
摘要： In a photomultiplier of the present invention, a semiconductor device arranged in an envelope to oppose a photocathode is constituted by a semiconductor substrate of a first conductivity type, a carrier multiplication layer of a second conductivity type different from the first conductivity type, which is formed on the semiconductor substrate by opitaxial growth, a breakdown voltage control layer of the second conductivity type, which is formed on the carrier multiplication layer and has a dopant concentration higher than that of the carrier multiplication layer, a first insulating layer formed on the breakdown voltage control layer and said carrier multiplication layer while partially exposing the surface of the breakdown voltage control layer as a receptor for photoelectrons and consisting of a nitride, and an ohmic electrode layer formed on a peripheral surface portion of the receptor of the breakdown voltage control layer. When the dopant concentration distribution in the carrier multiplication layer is uniformly controlled on the basis of epitaxial growth, the uniformity of an avalanche multiplication gain for photoelectrons incident at different positions on the receptor of the semiconductor device is improved, thereby largely increasing the energy resolving power.
摘要翻译：在本发明的光电倍增器中，布置在外壳中以与光电阴极相对的半导体器件由第一导电类型的半导体衬底，不同于第一导电类型的第二导电类型的载流子倍增层构成，形成在所述半导体衬底上通过外延生长形成第二导电类型的击穿电压控制层，所述第二导电类型的击穿电压控制层形成在所述载体倍增层上并且具有高于载流子倍增层的掺杂剂浓度的第一绝缘层，控制层和所述载体倍增层，同时部分地暴露作为光电子的受体的击穿电压控制层的表面，并由氮化物和形成在击穿电压控制层的受体的外围表面部分上的欧姆电极层组成。当基于外延生长均匀地控制载体倍增层中的掺杂剂浓度分布时，提高入射在半导体器件的接收器上的不同位置处的光电子的雪崩倍增益的均匀性，从而大大提高能量分辨能力。

10. 发明授权

US4805695A Counterflow heat exchanger with floating plate 失效
标题翻译：逆流换热器带浮板
公开(公告)号：US4805695A
公开(公告)日：1989-02-21
申请号：US150658
申请日：1987-12-23
申请人： Yoshitaka Ishikawa , Takeo Matsumoto
发明人： Yoshitaka Ishikawa , Takeo Matsumoto
IPC分类号： F28F3/04 , F28D9/00 , F28F3/10 , F28F9/007 , F28F3/00
CPC分类号： F28D9/00 , F28D9/0037 , Y10S165/393
摘要： Counterflow heat exchanger with a floating plate, which comprises a casing made of a pair of rectangular parallel-spaced wall members and four pieces of bar members connecting the corresponding corners of the pair of wall members, a pair of seal strips located inside said bar members through elastic members diagonally with regard to a line connecting the centers of the wall members, being extended so as to cover and seal a pair of the sides formed by a longer side of the wall members and the bar members, leaving a part of the sides uncovered. More than two sheets of floating plates are spaced apart from each other contained in a space formed by the seal strips and wall members. A spacer in a channel is formed between the floating plates, and a structure for controlling the flow of fluids within the channels is included. By making fluids having different temperatures flow countercurrently to each other through the channels, efficiency of heat exchange of the heat exchanger can be improved. The construction affords easy assembly and also a compact form.

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