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1. 发明授权

US5142490A Multiplication circuit with storing means 失效
标题翻译：具有存储装置的乘法电路
公开(公告)号：US5142490A
公开(公告)日：1992-08-25
申请号：US617440
申请日：1990-11-19
申请人： Yoshiki Tsujihashi , Kazuhiro Sakashita
发明人： Yoshiki Tsujihashi , Kazuhiro Sakashita
IPC分类号： G06F7/533 , G06F7/508 , G06F7/52 , G06F7/527 , G06F7/53
CPC分类号： G06F7/5312 , G06F2207/3884
摘要： The multiplication circuit is formed in such a manner that the intermediate sums of partial products are divided into a lower places group and a higher places group and the operations for obtaining the products of the lower places group alone of the intermediate sums already found are carried out parallel to the processing for obtaining the higher places group of the intermediate sums to obtain the higher products thereafter, noting to the fact that the intermediate sums of partial products are found sequentially from lower places to higher places. By adopting such an arrangement, the operations for obtaining the higher places group of the intermediate sums can be processed in parallel with the operations for obtaining the products of the lower places group of the intermediate sums already found, and the higher products are found thereafter. Therefore, the time required for the former-stage processing and that required for the latter-stage processing can be made more uniform.
摘要翻译：乘法电路形成为使得部分乘积的中间和被分成较低的位置组和较高的位置组，并且仅执行已经找到的中间和的单个下位组的乘积的操作平行于获得中间金额的较高地区组的处理以获得其后的较高产品，注意到从较低的地方到更高的地方依次找到部分产品的中间数量的事实。通过这样的安排，可以与获得已经找到的中间数量的下位组的产品的操作并行地获得用于获得中间数额的较高地方组的操作，并且之后发现较高的产品。因此，可以使后期处理所需的时间和后期处理所需的时间更均匀。

2. 发明授权

US5060183A Parallel multiplier circuit using matrices, including half and full adders 失效
标题翻译：使用矩阵的并行乘法器电路，包括一半和全加器
公开(公告)号：US5060183A
公开(公告)日：1991-10-22
申请号：US655229
申请日：1991-02-12
申请人： Kazuhiro Sakashita , Yoshiki Tsujihashi
发明人： Kazuhiro Sakashita , Yoshiki Tsujihashi
IPC分类号： G06F7/52
CPC分类号： G06F7/533
摘要： A parallel multiplier utilizing arrays of logic cells. A first circuit logic array forms and sums partial products of the most significant bits of the multiplicand with the multiplier. A second logic array forms and sums partial products of the least significant bits of the multiplier. A third circuit logic array which adds results of the partial product addition performed in parallel by the first and second circuit logic arrays. Since the first and second logic groups execute, respectively, the partial product addition in parallel, the number of adding steps is reduced as a whole and the operation speed is improved. The third logic array is disposed between the first and second logic arrays, resulting in a reasonable structure for circuit integrations and further improving system speed.
摘要翻译：使用逻辑单元阵列的并行乘法器。第一电路逻辑阵列形成并乘以被乘数的最高有效位与乘法器的部分乘积。第二个逻辑阵列形成并求和乘法器的最低有效位的部分乘积。第三电路逻辑阵列，其添加由第一和第二电路逻辑阵列并行执行的部分乘积加法的结果。由于第一和第二逻辑组分别执行部分乘积并行，所以增加步骤的数量整体上减少，并且提高了操作速度。第三逻辑阵列设置在第一和第二逻辑阵列之间，导致用于电路集成的合理结构并进一步提高系统速度。

3. 发明授权

US5911039A Integrated circuit device comprising a plurality of functional modules each performing predetermined function 失效
标题翻译：集成电路装置，包括各自执行预定功能的多个功能模块
公开(公告)号：US5911039A
公开(公告)日：1999-06-08
申请号：US787333
申请日：1997-01-27
申请人： Takeshi Hashizume , Kazuhiro Sakashita
发明人： Takeshi Hashizume , Kazuhiro Sakashita
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G06F11/267 , G06F11/27
CPC分类号： G01R31/318558
摘要： An integrated circuit device is structured by a plurality of functional modules (2a, 2b) each performing a predetermined function, each functional module including a test circuit (3) for testing the corresponding module. Each test circuit comprises a scan path (3a-3d) for receiving test data from a single common input line to perform a test and outputting a test output, a tri-state buffer (4a) for controlling an output of the test output from the scan path to a single common output line, and a scan path selecting circuit (5a) for selectively driving the tri-state buffer. All the selecting circuits in the integrated circuit device are connected in series to constitute as a whole a shift register. A selecting signal of the serial data is inputted to the shift register, so that the test output of each scan path is selectively supplied to the common output line.
摘要翻译：集成电路装置由各自执行预定功能的多个功能模块（2a，2b）构成，每个功能模块包括用于测试相应模块的测试电路（3）。每个测试电路包括用于从单个公共输入线接收测试数据以执行测试并输出测试输出的扫描路径（3a-3d），用于控制测试输出的输出的三态缓冲器（4a）扫描路径到单个公共输出线，以及扫描路径选择电路（5a），用于选择性地驱动三态缓冲器。集成电路装置中的所有选择电路串联连接构成移位寄存器。将串行数据的选择信号输入到移位寄存器，使得每个扫描路径的测试输出被选择性地提供给公共输出线。

4. 发明授权

US4995039A Circuit for transparent scan path testing of integrated circuit devices 失效
标题翻译：集成电路器件透明扫描路径测试电路
公开(公告)号：US4995039A
公开(公告)日：1991-02-19
申请号：US247289
申请日：1988-09-22
申请人： Kazuhiro Sakashita , Ichiro Tomioka , Takeshi Hashizume
发明人： Kazuhiro Sakashita , Ichiro Tomioka , Takeshi Hashizume
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/66
CPC分类号： G01R31/318552
摘要： In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.
摘要翻译：在用于测试集成电路器件的电路中，扫描寄存器（8差分16）和数据选择电路（20-28）根据数据的位数连接在多个电路块（29差分31）之间，扫描寄存器通过移位寄存器路径彼此连接，从而整体上具有一个移位寄存器的功能。寄存器选择电路（20差分28）连接到扫描寄存器的时钟输入端（T1，T2）。除了与要测试的逻辑电路块相对应的扫描寄存器之外的扫描寄存器由寄存器选择电路选择。因此，消除了除所需电路块之前和之后提供的扫描寄存器之外的扫描寄存器的时钟，从而可以减少扫描测试所需的时间。

5. 发明授权

US4780666A Semiconductor integrated circuit device having rest function 失效
标题翻译：具有休息功能的半导体集成电路器件
公开(公告)号：US4780666A
公开(公告)日：1988-10-25
申请号：US81256
申请日：1987-08-03
申请人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
发明人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G11C19/28 , G01R15/12
CPC分类号： G01R31/318541
摘要： A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.
摘要翻译：半导体集成电路器件包括设置在相邻电路块之间的多个锁存电路。每个锁存电路用于在电路设备的正常操作期间将来自前一电路块的输出数据直接传送到后续电路块，以保持输出数据直到扫描相关扫描寄存器并将其提供给后续电路块扫描模式，并且在测试操作的测试模式中与外部时钟同步地输出输出数据。

6. 发明授权

US4644500A Semiconductor memory device with a controlled precharging arrangement 失效
标题翻译：具有受控预充电布置的半导体存储器件
公开(公告)号：US4644500A
公开(公告)日：1987-02-17
申请号：US638677
申请日：1984-08-08
申请人： Ryo Yonezu , Kazuhiro Sakashita
发明人： Ryo Yonezu , Kazuhiro Sakashita
IPC分类号： G11C11/417 , G11C7/12 , G11C11/41 , G11C11/412 , G11C11/419 , H01L27/10 , G11C13/00
CPC分类号： G11C11/412 , G11C11/419 , G11C7/12
摘要： A semiconductor memory device includes: a memory cell constituted by MOSFETs; a bit line for transmitting a writing and a reading information to or from the memory cell therethrough; a writing-in control signal line for controlling the writing operation onto the memory cell; a first conductive type MOSFET with a source thereof being connected to a power supply terminal, with a gate thereof being connected to the writing-in control signal line, and with a drain thereof being connected to the bit line; the first conductive type MOSFET being adapted to charge up the bit line when no writing is performed in the memory cell; a second conductive type MOSFET with first control line thereof being connected to the bit line, with a gate thereof being connected to the writing-in control signal line, and with a second control line thereof being connected to the output terminal of the writing circuit; and the second conductive type MOSFET being adapted to transmit to the bit line an output from the writing circuit.
摘要翻译：半导体存储器件包括：由MOSFET构成的存储单元; 用于通过其向存储器单元发送写入和读取信息的位线; 写入控制信号线，用于控制对存储单元的写入操作; 第一导电型MOSFET，其源极连接到电源端子，其栅极连接到写入控制信号线，并且其漏极连接到位线; 所述第一导电型MOSFET适于在所述存储单元中不执行写入时对所述位线进行充电; 第二导电型MOSFET，其第一控制线连接到位线，其栅极连接到写入控制信号线，并且其第二控制线连接到写入电路的输出端; 并且所述第二导电型MOSFET适于向所述位线传输来自所述写入电路的输出。

7. 发明授权

US6032246A Bit-slice processing unit having M CPU's reading an N-bit width data element stored bit-sliced across M memories 失效
标题翻译：位片处理单元，其具有M个CPU读取在M个存储器中位分片存储的N位宽数据元素
公开(公告)号：US6032246A
公开(公告)日：2000-02-29
申请号：US45863
申请日：1998-03-23
申请人： Kazuhiro Sakashita
发明人： Kazuhiro Sakashita
IPC分类号： G06F9/38 , G06F15/80 , G06F9/00
CPC分类号： G06F15/8007
摘要： An object is to compatibly improve processing speed and storage capacity of semiconductor memory that the operation portion can use. Each of units (10a, 10b) each having an operation portion (11) and a memory portion (12) is formed of a single semiconductor chip. A data signal is separately stored in the two memory portions (12) in a bit-sliced form and each of the two operation portions (11) can use the 32-bit-wide data signal stored in the entirety of the two memory portions (12) through interconnections (22, 23). That is to say, each operation portion (11) can use a storage capacity twice larger than the capacity that can be ensured in a single semiconductor chip. Provided as interconnections for coupling the semiconductor chips are only the interconnections (22, 23) for transferring data signals from the two memory portions to the two operation portions (11). Hence, the bit width of the interconnections (22, 23) can be increased to increase the transmission speed of the data signals and to increase the processing speed of the device.
摘要翻译：目的是兼容地提高操作部可以使用的半导体存储器的处理速度和存储容量。每个具有操作部分（11）和存储部分（12）的单元（10a，10b）由单个半导体芯片形成。数据信号以位分片形式分别存储在两个存储器部分（12）中，并且两个操作部分（11）中的每一个可以使用存储在两个存储器部分的整体中的32位宽数据信号 12）通过互连（22,23）。也就是说，每个操作部分（11）可以使用比在单个半导体芯片中可以确保的容量大两倍的存储容量。提供用于耦合半导体芯片的互连仅用于将数据信号从两个存储器部分传送到两个操作部分（11）的互连（22,23）。因此，可以增加互连（22,23）的位宽度，以增加数据信号的传输速度并增加设备的处理速度。

8. 发明授权

US5130647A Scan test circuit and semiconductor integrated circuit device using the same 失效
标题翻译：使用相同的扫描测试电路和半导体集成电路器件
公开(公告)号：US5130647A
公开(公告)日：1992-07-14
申请号：US641195
申请日：1991-01-14
申请人： Kazuhiro Sakashita , Takeshi Hashizume
发明人： Kazuhiro Sakashita , Takeshi Hashizume
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/318541 , G01R31/318558
摘要： A data scan test circuit includes first through fourth latch circuits (L10 through L40). Data are latched in the third latch circuit (L40). A scan register consisting of the first, second and fourth latch circuits (L10, L20, L30) which become necessary when circuit blocks (CB1, CB2) are tested is made effective. Thus, unnecessary scan registers are put in the "through" state, thereby substantially reducing the number or scan paths in scan operation, and shortening the test time.
摘要翻译：数据扫描测试电路包括第一至第四锁存电路（L10至L40）。数据被锁存在第三锁存电路（L40）中。由测试电路块（CB1，CB2）时变得必需的第一，第二和第四锁存电路（L10，L20，L30）组成的扫描寄存器有效。因此，不必要的扫描寄存器被置于“通”状态，从而大大减少了扫描操作中的数量或扫描路径，缩短了测试时间。

9. 发明授权

US5109190A Semiconductor apparatus including semiconductor integrated circuit and operating method thereof 失效
标题翻译：半导体器件包括半导体集成电路及其工作方法
公开(公告)号：US5109190A
公开(公告)日：1992-04-28
申请号：US658032
申请日：1991-02-22
申请人： Kazuhiro Sakashita , Takeshi Hashizume
发明人： Kazuhiro Sakashita , Takeshi Hashizume
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/318555
摘要： A semiconductor apparatus including a semiconductor integrated circuit is disclosed. The semiconductor integrated circuit includes a circuit block, a plurality of boundary scan registers, a system data terminal, a test signal terminal and a control circuit. The control circuit responds to a test signal to generate control signals (a select signal LT, shift clock signals SCLK1 and SCLK2, a capture clock signal CPCLK and an update clock signal UPCLK) for controlling the boundary scan registers. The boundary scan registers are connected in cascade to each other and each connected to the circuit block. Each boundary scan register includes a selector circuit (12) and latch circuits (13, 14, 15). The latch circuit (13) responds to the shift clock signal SCLK1 to shift data of an adjacent preceding boundary scan register, an also responds to the update clock signal UPCLK to capture data from the selector circuit (12). The selector circuit (12) responds to the select signal LT to select system data or test data. The latch circuit (14) responds to the shift clock signal SCLK2 to shift the captured data to an adjacent succeeding boundary scan register. The latch circuit (15) responds only to the update clock signal UPCLK to apply the selected data to the circuit block.

10. 发明授权

US4638461A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4638461A
公开(公告)日：1987-01-20
申请号：US638678
申请日：1984-08-08
申请人： Ryo Yonezu , Kazuhiro Sakashita
发明人： Ryo Yonezu , Kazuhiro Sakashita
IPC分类号： G11C11/417 , G11C11/41 , G11C11/419 , H01L27/10 , G11C11/40
CPC分类号： G11C11/419
摘要： A semiconductor memory device, which comprises: a memory cell constituted by MOSFETs; a bit line for transmitting a writing and a reading information to the memory cell therethrough; a writing-in control signal line for controlling the writing operation onto the memory cell; and a writing circuit for transmitting the writing information input from the outside to the bit line at the time of writing but raising the voltage of the bit line up to a power supply voltage at the time of non-writing.
摘要翻译：一种半导体存储器件，包括：由MOSFET构成的存储单元; 用于将写入和读取信息发送到存储器单元的位线; 写入控制信号线，用于控制对存储单元的写入操作; 以及写入电路，用于在写入时将从外部输入的写入信息发送到位线，而在写入时将位线的电压提高到电源电压。

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