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1. 发明授权

US4992845A Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line 失效
标题翻译：具有输入/输出缓冲单元的半导体集成电路器件，每个单元包括排列成一行的多个晶体管区域
公开(公告)号：US4992845A
公开(公告)日：1991-02-12
申请号：US294020
申请日：1989-01-06
申请人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
发明人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
IPC分类号： H01L21/82 , H01L27/118
CPC分类号： H01L27/11898
摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).
摘要翻译：在半导体芯片（1）的中央部分设置有内部逻辑门部（3），设置有用于包围内部逻辑门部（3）的输入/输出缓冲器（4），并且提供接合焊盘（2）在对应于输入/输出缓冲器中的输入/输出缓冲单元（5）的半导体芯片（1）的外围部分中。每个输入/输出缓冲器单元（5）包括输出P-MOS部分（6），输出N-MOS部分（7），输入/逻辑P-MOS部分（8）和输入/ MOS部分（9），它们在从接合焊盘（2）到内部逻辑门部分（3）的方向上分别布置成单行。在上述结构中，键合焊盘（2）的焊盘布置方向上的输入/输出缓冲单元（5）中的每一个的尺寸减小，从而可以根据减少每个输入/输出缓冲单元（5）所需的排列方向的空间的使用。

2. 发明授权

US4864579A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4864579A
公开(公告)日：1989-09-05
申请号：US81094
申请日：1987-08-03
申请人： Satoru Kishida , Kazuhiro Sakashita , Ichiro Tomioka
发明人： Satoru Kishida , Kazuhiro Sakashita , Ichiro Tomioka
IPC分类号： G06F11/16 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/318541
摘要： A semiconductor integrated circuit device for transmitting data between a plurality of circuit blocks at least one thereof including a sequential circuit and enabling the circuit blocks to test in a scan testing type which has a plurality of scan registers provided between the plurality of circuit blocks corresponding to the number of bits of data to be transmitted for outputting the output data of the previous stage circuit block as it is at ordinary operating time and for holding and outputting the output data of the previous circuit block or test data for scan test synchronously with an external clock at testing time so that the circuits are connected by a shift register pass in such a manner that the entirety has one shaft register function, and a latch circuit provided at its data input terminal to the data output terminal of the corresponding scan register for outputtting the output data of the corresponding scan register as it is to the circuit block of next stage at ordinary operation time and holding the output data of the corresponding scan register before the scanning operation in a scan mode at testing time to continuously apply the data to the circuit block of next stage and holding and outputting the output data of the corresponding scan register in a test mode synchronously with the external clock, test data setting means for setting serial data of test from the exterior of the circuit device to each of the scan registers, test result outputting means for sequentially outputting the data of each scan register as serial data out of the circuit device, and operation switching means for switching the ordinary operation and the testing operation and switching the scan mode and the test mode, thereby enabling the semiconductor integrated circuit device to be readily subjected to a scan test together with circuit blocks including asynchronous sequential circuits.
摘要翻译：一种半导体集成电路装置，用于在多个电路块之间传输数据，其中至少一个电路块包括时序电路，并使电路块能够以扫描测试类型进行测试，该扫描测试类型具有多个扫描寄存器，该扫描寄存器设置在与要发送的数据的比特数，用于在正常操作时间输出前一级电路块的输出数据，并且用于保持和输出前一个电路块的输出数据或与外部的同步的扫描测试的测试数据时钟，使得电路通过移位寄存器通过连接，使得整体具有一个轴寄存器功能，以及锁存电路，在其数据输入端提供到相应扫描寄存器的数据输出端，用于输出相应的扫描寄存器的输出数据与普通操作下一级的电路块相同并且在测试时间内以扫描模式扫描操作之前保持相应扫描寄存器的输出数据，以将数据连续地施加到下一级的电路块，并在测试中保存和输出相应的扫描寄存器的输出数据与外部时钟同步的模式的测试数据设置装置，用于将测试的串行数据从电路设备的外部设置到每个扫描寄存器;测试结果输出装置，用于将每个扫描寄存器的数据顺序地输出为电路装置和用于切换普通操作和测试操作以及切换扫描模式和测试模式的操作切换装置，从而使得半导体集成电路器件能够容易地与包括异步时序电路的电路块一起进行扫描测试。

3. 发明授权

US5568068A Buffer circuit for regulating driving current 失效
标题翻译：用于调节驱动电流的缓冲电路
公开(公告)号：US5568068A
公开(公告)日：1996-10-22
申请号：US534114
申请日：1995-09-26
申请人： Yoshiyuki Ota , Ichiro Tomioka , Eiji Murakami
发明人： Yoshiyuki Ota , Ichiro Tomioka , Eiji Murakami
IPC分类号： H03K19/0175 , G11C11/409 , H03F1/56 , H03K19/003
CPC分类号： H03K19/00323
摘要： A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied. A buffer circuit with driving current adjusting function of the present invention comprises a buffer circuit which is controlled by a control signal for supplying a most appropriate driving current to a load; a load detecting circuit for detecting a phase difference between an input signal and an output signal of the buffer circuit and for outputting voltage corresponding to the phase difference, a control signal generating circuit for generating a signal which controls the driving current of the buffer circuit in response to an output signal of the load detecting circuit, the control signal controls so that the driving current of buffer circuit is increased when delay time of buffer circuit becomes long and the driving current of buffer circuit is decreased when delay time becomes short.
摘要翻译：提供具有驱动电流调节功能的缓冲电路，其可以根据要施加驱动电流的系统自动将缓冲器的驱动电流特性设置为最合适的值。具有本发明的驱动电流调节功能的缓冲电路包括缓冲电路，该缓冲电路由用于向负载提供最合适的驱动电流的控制信号控制; 负载检测电路，用于检测输入信号和缓冲电路的输出信号之间的相位差并输出与相位差相对应的电压;控制信号发生电路，用于产生控制缓冲电路的驱动电流的信号响应于负载检测电路的输出信号，当延迟时间变短时，缓冲电路的延迟时间变长，缓冲电路的驱动电流减小时，控制信号进行控制，使得缓冲电路的驱动电流增加。

4. 发明授权

US5552618A Multi-voltage-lever master-slice integrated circuit 失效
公开(公告)号：US5552618A
公开(公告)日：1996-09-03
申请号：US326086
申请日：1994-10-19
申请人： Hideki Taniguchi , Ichiro Tomioka , Kunihiko Sanada , Masatomi Okabe
发明人： Hideki Taniguchi , Ichiro Tomioka , Kunihiko Sanada , Masatomi Okabe
IPC分类号： H01L21/82 , H01L27/118 , H01L27/10 , H01L27/02
CPC分类号： H01L27/11898 , H01L2224/05554
摘要： A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.

5. 发明授权

US4916385A Inverter circuit 失效
标题翻译：逆变电路
公开(公告)号：US4916385A
公开(公告)日：1990-04-10
申请号：US262302
申请日：1988-10-25
申请人： Ichiro Tomioka , Masahiro Ueda , Takahiko Arakawa , Toshiaki Hanibuchi , Yoshihiro Okuno
发明人： Ichiro Tomioka , Masahiro Ueda , Takahiko Arakawa , Toshiaki Hanibuchi , Yoshihiro Okuno
IPC分类号： G01R19/165 , G01R31/316 , G01R31/317 , G01R31/319 , H03K17/00 , H03K17/16 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00361 , G01R31/316 , G01R31/31905
摘要： An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.
摘要翻译：公开了一种逆变器电路（I3），其包括串联连接在电源（VDD）和地（GND）之间的P沟道MOSFET（3）和N沟道MOSFET（4）。逆变器电路还包括在FET（3）和（4）的栅极之间并联连接的P沟道MOSFET（5）和N沟道MOSFET（6）。 FET（3）和（4）的栅极连接以接收测试模式信号（TE）。在测试模式操作中，使FET（6）导通以允许通过FET（6）将输入信号施加到FET（4）的栅极。响应于通过FET（6）施加的输出信号，具有低于FET（3）的导通电阻的FET（4）被驱动成导通，从而提供缓慢上升的输出信号。缓慢上升的输出信号没有下冲或振铃。

6. 发明授权

US4870345A Semiconductor intergrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4870345A
公开(公告)日：1989-09-26
申请号：US81095
申请日：1987-08-03
申请人： Ichiro Tomioka , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Takahiko Arakawa
发明人： Ichiro Tomioka , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Takahiko Arakawa
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536
摘要： A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.
摘要翻译：半导体集成电路包括级联异步顺序逻辑电路。在异步时序电路之间提供扫描移位寄存器，以允许将测试数据应用于电路的输入，并根据测试数据锁存和移出由电路提供的输出数据。在扫描移位寄存器和异步顺序电路的输入之间提供附加的选通电路，以防止锁存在扫描移位寄存器中的新数据使测试期间连接到扫描移位寄存器输出的异步时序电路变化。可以使用相同的附加电路来响应于外部产生的门控控制信号来提供受控宽度和/或定时到异步顺序电路输入的脉冲。

7. 发明授权

US4856002A Semiconductor integrated circuit apparatus 失效
标题翻译：半导体集成电路装置
公开(公告)号：US4856002A
公开(公告)日：1989-08-08
申请号：US062439
申请日：1987-06-12
申请人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
发明人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/31816 , G01R31/318533
摘要： A test circuit of a semiconductor integrated circuit apparatus comprising a latch circuit connected to an output terminal of a scan register for holding output data of the scan register stored before scanning in a scan mode during the test operation.
摘要翻译：一种半导体集成电路装置的测试电路，包括连接到扫描寄存器的输出端的锁存电路，用于在测试操作期间以扫描模式保持在扫描之前存储的扫描寄存器的输出数据。

8. 发明授权

US4072016A Method of reconstructing and reclamation of river channels 失效
标题翻译：河道重建和开垦方法
公开(公告)号：US4072016A
公开(公告)日：1978-02-07
申请号：US742540
申请日：1976-11-17
申请人： Kiyoshi Seki , Ichiro Tomioka , Yoshihiko Sawa
发明人： Kiyoshi Seki , Ichiro Tomioka , Yoshihiko Sawa
IPC分类号： E02B3/00 , E02F5/22 , E02B3/04
CPC分类号： E02B3/00 , E02F5/223
摘要： A method of reconstructing or reclaiming river channels which are partially filled with soft, slimy sedimentary deposits including industrial wastes which are in a semi-fluid condition or fluidized state comprising the steps of: demarcating a portion of the channel by placing a water tight wall entirely across the channel from bank to bank at an upstream and downstream location; depositing stable fill material adjacent the banks of the channel so as to displace the soft sedimentary deposits and water toward the center of the channel; and treating the displaced soft sedimentary deposit in situ beneath the overlying water so as to stabilize the entire mass.The channel may be completely reclaimed by pumping out the overlying water after the soft sedimentary deposit has been stabilized and then filling with stable material or stable material may be simply placed on the stabilized mass and the water displaced over the top of the downstream wall or over the adjacent bank.
摘要翻译：一种重建或回收河道的方法，其部分地填充有软的，粘稠的沉积沉积物，包括处于半流体状态或流化状态的工业废物，包括以下步骤：通过放置一个完全不透水的壁来界定通道的一部分跨越上游和下游地区的银行渠道; 在通道的堤岸附近沉积稳定的填充材料，以便将软沉积物和水移向通道的中心; 并在上层水下原位处理置换的软沉积沉积物，以稳定整个质量。

9. 发明授权

US5483479A Associative storage memory 失效
标题翻译：关联存储器
公开(公告)号：US5483479A
公开(公告)日：1996-01-09
申请号：US50850
申请日：1993-04-21
申请人： Nobuyuki Osawa , Ichiro Tomioka , Mitsuhiro Deguchi
发明人： Nobuyuki Osawa , Ichiro Tomioka , Mitsuhiro Deguchi
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A memory cell for an associative storage memory device includes a transmission gate which is rendered conductive or non-conductive in response to a potential on a word line for transferring information between an information hold circuit and a bit line or between the information hold circuit and an inverted bit line. Match line are precharged to ground and supply potentials, respectively, and, thereafter, a retrieval circuit compares information on the bit line or inverted bit line with information held in the information hold circuit and produces a control signal to control the potentials on the match lines in accordance with the result of comparison. After the match lines are precharged, a gating circuit is rendered conductive in response to potentials on output control line and inverted output control line to thereby couple the control signal to the match lines.
摘要翻译：用于关联存储存储器件的存储器单元包括传输门，其响应于字线上的电位而被导通或不导通，用于在信息保持电路和位线之间或在信息保持电路和信号保持电路之间传送信息反转位线。匹配线分别被预充电到接地和供电电位，之后，检索电路将有关位线或反向位线的信息与保存在信息保持电路中的信息进行比较，并产生控制信号以控制匹配线上的电位按照比较结果。在匹配线被预充电之后，门控电路响应于输出控制线和反相输出控制线上的电位而导通，从而将控制信号耦合到匹配线。

10. 发明授权

US5323070A Output buffer circuit having output bouncing controlled circuits 失效
标题翻译：输出缓冲电路，具有输出弹跳控制电路
公开(公告)号：US5323070A
公开(公告)日：1994-06-21
申请号：US821941
申请日：1992-01-17
申请人： Masahiro Ueda , Ichiro Tomioka
发明人： Masahiro Ueda , Ichiro Tomioka
IPC分类号： H03K17/16 , H03K17/687 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/092
CPC分类号： H03K19/01721 , H03K19/00361 , H03K19/09448
摘要： A first output buffer having a large current driving capability and a second output buffer having a small current driving capability are connected in parallel between an input terminal and an external lead. The first and second output buffers each includes two CMOS inverters connected in series between the input terminal and the external lead. The P-channel and N-channel MOSFETs of the two CMOS inverters in the second output buffer have gate widths smaller than each of the P-channel and N-channel MOSFETs, respectively, of the two CMOS inverters in the first output buffer. Also disclosed is an output buffer having P-channel and N-channel MOSFETs arranged as a CMOS inverter, but with a base of a first bipolar transistor connected to a source of the N-channel MOSFET. An emitter of the first bipolar transistor is connected to ground and its collector is connected to an output of the output buffer. A base of a second bipolar transistor is connected to an output of the CMOS inverter and its emitter is connected to the output of the output buffer. An input of the output buffer is supplied to an input of the CMOS inverter. Another transistor is connected between the output of the output buffer and ground and is responsive to the input of the output buffer.
摘要翻译：具有大电流驱动能力的第一输出缓冲器和具有小电流驱动能力的第二输出缓冲器并联连接在输入端和外部引线之间。第一和第二输出缓冲器各自包括串联连接在输入端和外部引线之间的两个CMOS反相器。第二输出缓冲器中的两个CMOS反相器的P沟道和N沟道MOSFET分别具有比第一输出缓冲器中的两个CMOS反相器的P沟道和N沟道MOSFET中的每一个的栅极宽度小的栅极宽度。还公开了具有布置为CMOS反相器但具有连接到N沟道MOSFET的源极的第一双极晶体管的基极的P沟道和N沟道MOSFET的输出缓冲器。第一双极晶体管的发射极连接到地，其集电极连接到输出缓冲器的输出端。第二双极晶体管的基极连接到CMOS反相器的输出，其发射极连接到输出缓冲器的输出端。输出缓冲器的输入被提供给CMOS反相器的输入。另一个晶体管连接在输出缓冲器的输出和地之间，并响应于输出缓冲器的输入。

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