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1. 发明申请

US20160219295A1 THRESHOLD FILTERING OF COMPRESSED DOMAIN DATA USING STEERING VECTOR 有权
标题翻译：使用转向矢量对压缩域数据进行阈值滤波
公开(公告)号：US20160219295A1
公开(公告)日：2016-07-28
申请号：US14607113
申请日：2015-01-28
申请人： Intel Corporation
发明人： SUDHIR K. SATPATHY , SANU K. MATHEW , RAM K. KRISHNAMURTHY
IPC分类号： H04N19/48 , G06T7/00 , H04N19/85 , G06F7/24
CPC分类号： G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
摘要： In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括耦合到多个核的压缩域阈值滤波器。压缩域阈值滤波器是：接收要滤波的压缩数据的采样向量; 至少基于样本矢量的元素的第一子集计算样本矢量和导向矢量的点积的估计上限值; 确定点积的估计上限值是否满足滤波器阈值; 并且响应于确定点积的估计上限值不满足滤波器阈值，而不完成样本矢量和导向矢量的点乘积的计算而丢弃样本矢量。描述和要求保护其他实施例。

2. 发明申请

US20150261500A1 VARIABLE-LATENCY SPECULATING PIPELINED BOOTH MULTIPLIER WITH STATISTICAL CARRY ESTIMATION FOR ERROR DETECTION AND RECOVERY 有权
标题翻译：具有统计检验估计和恢复能力的可变延迟分布式管道加油机
公开(公告)号：US20150261500A1
公开(公告)日：2015-09-17
申请号：US14204133
申请日：2014-03-11
申请人： NATIONAL CHIAO TUNG UNIVERSITY
发明人： Chih-Wei Liu , Shin-Kai Chen , Kuo-Chiang Chang , Tsung-Yi Wu , An-Chi Tsai
IPC分类号： G06F7/40
CPC分类号： G06F7/533
摘要： Provided is a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM), including a first operation and a second operation. The first operation has the steps of partitioning partial products into a least significant part (LSP) and a most significant part (MSP), estimating a carry of the LSP, computing the MSP based on the estimated carry, computing the LSP independently to obtain a true carry and detecting a computation error by comparing the estimated carry with the true carry. Also, the second operation has the step of correcting the computation error based on the difference between the estimated carry and the true carry. Further, a VLSBM for processing pipelined data is also provided.
摘要翻译：提供了一种使用可变延迟推测展位乘数（VLSBM）处理流水线数据的方法，包括第一操作和第二操作。第一操作具有将部分产品划分为最不重要部分（LSP）和最重要部分（MSP）的步骤，估计LSP的进位，基于估计的进位计算MSP，独立地计算LSP以获得通过将估计的进位与真实进位进行比较来真实携带并检测计算误差。此外，第二操作具有基于估计的进位和真实进位之间的差来校正计算误差的步骤。此外，还提供了用于处理流水线数据的VLSBM。

3. 发明申请

US20150235634A1 ASYMMETRIC CIRCUITRY 有权
标题翻译：不对称电路
公开(公告)号：US20150235634A1
公开(公告)日：2015-08-20
申请号：US14183321
申请日：2014-02-18
申请人： Apple Inc.
发明人： Michael L. Liu , Liang Deng
IPC分类号： G09G5/395 , H03K19/173 , H03K19/00
CPC分类号： G09G5/395 , G06F7/533 , H03K19/0013 , H03K19/1737
摘要： Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.
摘要翻译：公开了涉及不对称电路的技术。在一些实施例中，存储元件被配置为在时间间隔期间将第一输入值保持为非对称电路的输入。例如，在一个实施例中，时间间隔可以对应于视频数据的帧，并且存储元件可以被配置为存储用于视频数据帧的滤波器系数。在一些实施例中，存储元件可以被配置为将该值存储为用于由非对称电路进行的多个操作的常数。在一些实施例中，非对称电路被配置为基于第一输入值和一组第二输入值中的相应值来产生多个输出值。在一些实施例中，非对称电路是泄漏功率不对称和/或关键路径不对称。这可能会提高性能和/或降低功耗。

4. 发明申请

US20130262544A1 ELECTRONIC MULTIPLIER AND DIGITAL SIGNAL PROCESSOR INCLUDING THE SAME 审中-公开
标题翻译：电子乘法器和数字信号处理器，包括它们
公开(公告)号：US20130262544A1
公开(公告)日：2013-10-03
申请号：US13716994
申请日：2012-12-17
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yong-Ki Lee , Jong-Hoon Shin , Kyoung-Moon Ahn , Ji-Su Kang , Sun-Soo Shin
IPC分类号： G06F7/533 , G06F7/58
CPC分类号： G06F7/533 , G06F7/5324 , G06F7/5338 , G06F7/588 , G06F2207/7257
摘要： An electronic multiplier, such as a multiplication circuit, may include a partial product generator, a Booth code encoder and an accumulator. The partial product generator may generate partial product data based on a Booth code and multiplicand data. The Booth code encoder may generate the Booth code based on multiplier data. The Booth code may include a zero-generation Booth code and a zero-avoidance Booth code. The Booth code encoder may selectively generate the zero-generation Booth code or the zero-avoidance Booth code when the partial product data correspond to a partial product of zero. The accumulator accumulates the partial product data to provide a multiplication result of the multiplicand data and the multiplier data.
摘要翻译：诸如乘法电路的电子倍增器可以包括部分乘积发生器，布斯码编码器和累加器。部分积发生器可以基于布斯码和被乘数数据生成部分乘积数据。布斯码编码器可以基于乘数数据生成布斯码。展位代码可以包括零代布斯代码和零回避布斯码。当部分乘积数据对应于零的部分乘积时，布斯克编码器可以选择性地生成零代布斯码或零回避布斯码。累加器积累部分乘积数据以提供被乘数数据和乘数数据的相乘结果。

5. 发明授权

US07139787B2 Multiply execution unit for performing integer and XOR multiplication 有权
标题翻译：乘以执行整数和XOR乘法的执行单元
公开(公告)号：US07139787B2
公开(公告)日：2006-11-21
申请号：US10354354
申请日：2003-01-30
申请人： Leonard D. Rarick , Sheueling Chang Shantz , Shreyas Sundaram
发明人： Leonard D. Rarick , Sheueling Chang Shantz , Shreyas Sundaram
IPC分类号： G06F7/52 , G06F15/00
CPC分类号： G06F7/724 , G06F7/533
摘要： A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The partial products may be Booth encoded. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a first plurality of full adders. The first plurality of full adders each has three inputs, a carry output, and a sum output. The sum outputs of the first plurality of full adders are independent of the value of any carry output in the summing circuit. The summing circuit also includes a second plurality of full adders. The second plurality of full adders each has three inputs, a carry output, and a sum output. The XOR sum is dependent upon at least one of the sum outputs of the first plurality of full adders but is independent of the sum outputs of the second plurality of full adders. The integer sum is dependent upon the sum outputs of at least one of the first plurality of full adders and is also dependent on at least one of the sum outputs of the second plurality of full adders.
摘要翻译：乘法执行单元，其可操作以生成乘积和乘法器和乘法器的XOR乘积。乘法执行单元包括用于求和多个部分乘积的求和电路。部分产品可能是布斯编码的。求和电路可以生成多个部分乘积的整数，并且可以产生多个部分乘积的XOR和。求和电路包括第一多个完全加法器。第一组多个全加器各有三个输入，一个进位输出和一个和输出。第一多个完全加法器的和输出与求和电路中的任何进位输出的值无关。求和电路还包括第二多个完全加法器。第二组多个全加器各具有三个输入，一个进位输出和一个和输出。 XOR和取决于第一多个完全加法器的和输出中的至少一个，但是与第二多个完全加法器的和输出无关。整数和取决于第一多个全加法器中的至少一个的总和输出，并且还取决于第二多个完全加法器的和输出中的至少一个。

6. 发明申请

US20050080834A1 Fused booth encoder multiplexer 失效
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US20050080834A1
公开(公告)日：2005-04-14
申请号：US10675674
申请日：2003-09-30
申请人： Wendy Belluomini , Hung Ngo , Jun Sawada
发明人： Wendy Belluomini , Hung Ngo , Jun Sawada
IPC分类号： G06F7/52 , G06F7/544
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit. The fused Booth encoder multiplexer unit, tree unit and adder unit function in a pipeline manner with the units operating on sequential data sets during a given processing cycle. The fused Booth encoder multiplexer unit may be advantageously laid out in a design of an integrated circuit chip with no gap present in the layout, which allows uniform wire length and avoids the necessity of large transistors to drive long interconnection wires.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。融合的布尔编码器多路复用器单元，树形单元和加法器单元在给定的处理周期内以流水线方式与在顺序数据集上操作的单元进行功能。融合布尔编码器多路复用器单元可有利地布置在集成电路芯片的设计中，布局中不存在间隙，这允许均匀的导线长度，并避免了大晶体管驱动长互连线的必要性。

7. 发明授权

US5600569A Method, system, and apparatus for automatically designing logic circuit, and multiplier 失效
标题翻译：用于自动设计逻辑电路的方法，系统和装置，以及乘法器
公开(公告)号：US5600569A
公开(公告)日：1997-02-04
申请号：US300802
申请日：1994-09-02
申请人： Tamotsu Nishiyama , Shintaro Tsubata
发明人： Tamotsu Nishiyama , Shintaro Tsubata
IPC分类号： G06F7/533 , G06F7/48 , G06F7/508 , G06F7/52 , G06F17/50
CPC分类号： G06F7/53 , G06F17/5045 , G06F7/52 , G06F7/533 , G06F7/4824
摘要： With respect to each bit of a multiplier factor, it is judged whether or not the multiplier factor is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a bit of concern in the multiplier factor has the value of 1. Only if the bit of concern in the multiplier factor is 1, there is generated a circuit for outputting, as a partial product, a signal indicating a multiplicand. The signal indicating the multiplicand is then shifted by one bit so that the resulting signal is newly set as the signal indicating the multiplicand. By repeatedly executing the foregoing process with respect to all the bits of the multiplier factor, a circuit for calculating a partial product with respect to each bit of the multiplier factor is generated.
摘要翻译：关于乘数的每一位，判断乘数是否为变量或常数。如果乘数是常数，则判断乘数中的一点关注值是否为1.只有当倍增系数中所涉及的位为1时，才产生输出电路，如部分乘积，指示被乘数的信号。然后，指示被乘数的信号被移位一位，使得结果信号被新设置为指示被乘数的信号。通过对乘法器系数的所有比特重复执行上述处理，生成用于计算相对于乘数因子的每个比特的部分乘积的电路。

8. 发明授权

US4910701A Split array binary multiplication 失效
标题翻译：分割数组二进制乘法
公开(公告)号：US4910701A
公开(公告)日：1990-03-20
申请号：US100802
申请日：1987-09-24
申请人： Jon C. Gibbons , Simon Y. C. Lau , Marvin N. Fox
发明人： Jon C. Gibbons , Simon Y. C. Lau , Marvin N. Fox
IPC分类号： G06F7/52
CPC分类号： G06F7/533 , G06F7/5338 , G06F7/49994
摘要： A system for binary multiplication based upon the modified Booth algorithm incorporating a Booth multiplex decoder, partial modified Booth arrays and partial product reduction adders. The system is comprised of Booth multiplexer cells, Booth multiplexer and adder cells, sign extension cells, and full adder cells interconnected such that the total adder delay through the system is n/4+1 adder delays where n is the number of bits in the multiplier.
摘要翻译：一种基于改进的布斯算法的二进制乘法系统，该布斯算法结合了布斯多路复用解码器，部分修正布阵列和部分乘积减法加法器。该系统由Booth多路复用器单元，Booth多路复用器和加法器单元，符号扩展单元和全加器单元互连，使得通过系统的总加法器延迟为n / 4 + 1个加法器延迟，其中n是乘数。

9. 发明授权

US4179734A Floating point data processor having fast access memory means 失效
标题翻译：具有快速存取存储装置的浮点数据处理器
公开(公告)号：US4179734A
公开(公告)日：1979-12-18
申请号：US846889
申请日：1977-10-31
申请人： George P. O'Leary
发明人： George P. O'Leary
IPC分类号： G06F7/50 , G06F7/52 , G06F7/57 , G06F9/38 , G06F13/06
CPC分类号： G06F7/5312 , G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/533 , G06F9/3879 , G06F2207/3884 , G06F2207/3896 , G06F7/49936 , G06F7/49947
摘要： A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle. Memory registers comprise a data pad having a plurality of selectable stack registers and means for writing information into said data pad during one clock cycle for retrieval during the next clock cycle.
摘要翻译：数字数据处理器包括多个存储器寄存器，浮点加法器和由多个可同时操作的并行总线相互耦合的浮点乘法器，其有助于在一个时钟周期或指令期间的多个并行操作。浮动加法器和乘法器各自包括由中间临时存储寄存器分隔的级数，其接收在下一个时钟周期期间由下一级使用的计算的部分结果。在每个时钟周期内产生浮点加法，乘法和其他算术和逻辑结果。存储器寄存器包括具有多个可选择的堆栈寄存器的数据焊盘和用于在一个时钟周期内将信息写入所述数据焊盘的装置，用于在下一个时钟周期期间进行检索。

10. 发明授权

US09607586B2 Asymmetric circuitry 有权
公开(公告)号：US09607586B2
公开(公告)日：2017-03-28
申请号：US14183321
申请日：2014-02-18
申请人： Apple Inc.
发明人： Michael L. Liu , Liang Deng
IPC分类号： G09G5/395 , H03K19/00 , G06F7/533 , H03K19/173
CPC分类号： G09G5/395 , G06F7/533 , H03K19/0013 , H03K19/1737
摘要： Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.

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