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1. 发明授权

US11836971B2 Method and device with convolution neural network processing 有权
公开(公告)号：US11836971B2
公开(公告)日：2023-12-05
申请号：US16549002
申请日：2019-08-23
申请人： Samsung Electronics Co., Ltd.
发明人： Mostafa Mahmoud , Andreas Moshovos
IPC分类号： G06N3/04 , G06F7/533 , G06K9/54 , G06K9/46 , G06K9/62 , G06V10/94 , G06F18/21 , G06V10/82 , G06V10/44
CPC分类号： G06V10/955 , G06F7/533 , G06F18/2163 , G06N3/04 , G06V10/454 , G06V10/82
摘要： A processor-implemented method implementing a convolution neural network includes: determining a plurality of differential groups by grouping a plurality of raw windows of an input feature map into the plurality of differential groups; determining differential windows by performing, for each respective differential group of the differential groups, a differential operation between the raw windows of the respective differential group; determining a reference element of an output feature map corresponding to a reference raw window among the raw windows by performing a convolution operation between a kernel and the reference raw window; and determining remaining elements of the output feature map by performing a reference element summation operation based on the reference element and each of a plurality of convolution operation results determined by performing respective convolution operations between the kernel and each of the differential windows.

2. 发明授权

US10635397B2 System and method for long addition and long multiplication in associative memory 有权
公开(公告)号：US10635397B2
公开(公告)日：2020-04-28
申请号：US15915113
申请日：2018-03-08
申请人： GSI Technology Inc.
发明人： Moshe Lazer
IPC分类号： G06F7/533 , G06F7/501
CPC分类号： G06F7/533 , G06F7/501
摘要： A method for an associative memory device includes replacing a set of three multi-bit binary numbers P, Q and R, stored in the associative memory device, with two multi-bit binary numbers X and Y, also stored in the associative memory device, wherein a sum of the binary numbers P, Q and R is equal to a sum of the binary numbers X and Y. A system includes an associative memory array having rows and columns and a multi-bit multiplier. Each column of the array stores two multi-bit binary numbers to be multiplied. The multi-bit multiplier multiplies, in parallel, the two multi-bit binary numbers per column by concurrently processing all bits of partial products generated by the multiplier. The multiplier performs the processing without any carry propagation delay when adding all but the last two partial products.

3. 发明授权

US09607586B2 Asymmetric circuitry 有权
公开(公告)号：US09607586B2
公开(公告)日：2017-03-28
申请号：US14183321
申请日：2014-02-18
申请人： Apple Inc.
发明人： Michael L. Liu , Liang Deng
IPC分类号： G09G5/395 , H03K19/00 , G06F7/533 , H03K19/173
CPC分类号： G09G5/395 , G06F7/533 , H03K19/0013 , H03K19/1737
摘要： Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.

4. 发明申请

US20170039034A1 THRESHOLD FILTERING OF COMPRESSED DOMAIN DATA USING STEERING VECTOR 审中-公开
标题翻译：使用转向矢量对压缩域数据进行阈值滤波
公开(公告)号：US20170039034A1
公开(公告)日：2017-02-09
申请号：US15296139
申请日：2016-10-18
申请人： Intel Corporation
发明人： SUDHIR K. SATPATHY , SANU K. MATHEW , RAM K. KRISHNAMURTHY
IPC分类号： G06F7/533
CPC分类号： G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
摘要： In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括耦合到多个核的压缩域阈值滤波器。压缩域阈值滤波器是：接收要滤波的压缩数据的采样向量; 至少基于样本矢量的元素的第一子集计算样本矢量和导向矢量的点积的估计上限值; 确定点积的估计上限值是否满足滤波器阈值; 并且响应于确定点积的估计上限值不满足滤波器阈值，而不完成样本矢量和导向矢量的点乘积的计算而丢弃样本矢量。描述和要求保护其他实施例。

5. 发明授权

US09459831B2 Fast computation of products by dyadic fractions with sign-symmetric rounding errors 有权
$Fast computation of products by dyadic fractions with sign-symmetric rounding errors$
标题翻译：通过具有符号对称舍入误差的二进制分数快速计算产品
公开(公告)号：US09459831B2
公开(公告)日：2016-10-04
申请号：US14332028
申请日：2014-07-15
申请人： QUALCOMM Incorporated
发明人： Yuriy Reznik
IPC分类号： G06F7/483 , G06F7/533 , G06F17/14 , H04N19/60 , H04N19/42 , G06F7/499
CPC分类号： G06F7/483 , G06F7/49942 , G06F7/533 , G06F17/147 , H04N19/42 , H04N19/60
摘要： A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.
摘要翻译：可以通过符号对称算法来确定整数值和非理性值的乘积。过程可以确定最小化度量的可能算法，例如平均不对称性，平均误差，误差方差和误差大小。给定一个整数变量x和近似非理性分数的有理二元常数，可以产生一系列中间值，这些中间值是符号对称的。中间值可以包括加法，减法和右移操作的序列，当加在一起近似整数和非理性值的乘积时。可以删除其他操作，例如0的加法或减法或0位的移位。

6. 发明授权

US09274751B2 Fused booth encoder multiplexer 有权
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US09274751B2
公开(公告)日：2016-03-01
申请号：US11776454
申请日：2007-07-11
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/533 , G06F7/483 , G06F7/544
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

7. 发明授权

US08229992B2 Fused booth encoder multiplexer 失效
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US08229992B2
公开(公告)日：2012-07-24
申请号：US11670357
申请日：2007-02-01
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

8. 发明授权

US07373368B1 Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication 有权
标题翻译：包括4：2和/或5：3压缩器的执行单元，用于执行整数和XOR乘法
公开(公告)号：US07373368B1
公开(公告)日：2008-05-13
申请号：US10891978
申请日：2004-07-15
申请人： Leonard D. Rarick , Shu-Chin Tai
发明人： Leonard D. Rarick , Shu-Chin Tai
IPC分类号： G06F7/52
CPC分类号： G06F7/724 , G06F7/533
摘要： A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The summing circuit includes a plurality of rows. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a plurality of compressors in the first row of the summing circuit. The plurality of compressors each has more than three inputs that receive data, a carry output, and a sum output.
摘要翻译：乘法执行单元，其可以生成被乘数和乘数的整数乘积，并且还可操作以产生被乘数和乘数的XOR乘积。乘法执行单元包括用于求和多个部分乘积的求和电路。求和电路包括多行。求和电路可以生成多个部分乘积的整数，并且可以产生多个部分乘积的XOR和。求和电路包括在求和电路的第一行中的多个压缩机。多个压缩机每个具有多于三个接收数据的输入，进位输出和和输出。

9. 发明授权

US06993551B2 Sparse-coefficient functions for reducing computational requirements 失效
公开(公告)号：US06993551B2
公开(公告)日：2006-01-31
申请号：US10122453
申请日：2002-04-12
申请人： J. William Whikehart , Christopher John Hagan
发明人： J. William Whikehart , Christopher John Hagan
IPC分类号： G06F7/52
CPC分类号： G06F7/533 , G06F5/01 , G06F7/607
摘要： A method for reducing computational steps in a digital processor including multiplications producing a plurality of multiplication products. This method specifies a desired multiplication function to be implemented in a digital processor, the desired multiplication function having a respective set of initial coefficients corresponding to each digital multiplier stage of the multiplication function. An initial total number of non-zero bits of the initial coefficients is determined and the initial coefficients are modified. Further, a resulting number of non-zero bits in the modified set of coefficients is quantified. Finally, the modified set of coefficients that result in a reduced number of non-zero bits as compared to the initial coefficients is chosen. The new modified coefficients are implemented in the device by constructing the digital multiplier stages with the modified coefficients. Thus, the digital processor performs a desired multiplication function using “sparse” coefficients to achieve a reduced execution time or lower implementation cost for a given signal conditioning function.

10. 发明申请

US20050050133A1 Switching activity reduced coding for low-power digital signal processing circuitry 失效
标题翻译：开关活动减少了低功耗数字信号处理电路的编码
公开(公告)号：US20050050133A1
公开(公告)日：2005-03-03
申请号：US10650641
申请日：2003-08-28
申请人： Christian Lutkemeyer
发明人： Christian Lutkemeyer
IPC分类号： G06F7/52 , G06F7/533 , H03H17/02
CPC分类号： G06F7/533 , G06F7/5336 , H03H17/0236 , H03H2017/0692
摘要： A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.
摘要翻译：一种通过减少这种电路中不必要的切换量来减少数字电路中的功耗的系统和方法。本发明的一个方面提供一种将信号输出到随后的数字电路的开关降低电路。信号的值可以取决于信号值与随后数字电路的下一个输出的相关性。根据本发明的各个方面的方法包括接收下一个输入信号。该方法还包括确定下一个输入信号是否可能与随后数字电路的下一个输出有关。该方法还包括当下一个输入信号可能与随后的数字电路的下一个输出相关时，向随后的数字电路提供下一个输入信号，并且当下一个输入信号不会与后续数字电路的下一个输出相关。

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