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1. 发明授权

US4780666A Semiconductor integrated circuit device having rest function 失效
标题翻译：具有休息功能的半导体集成电路器件
公开(公告)号：US4780666A
公开(公告)日：1988-10-25
申请号：US81256
申请日：1987-08-03
申请人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
发明人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G11C19/28 , G01R15/12
CPC分类号： G01R31/318541
摘要： A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.
摘要翻译：半导体集成电路器件包括设置在相邻电路块之间的多个锁存电路。每个锁存电路用于在电路设备的正常操作期间将来自前一电路块的输出数据直接传送到后续电路块，以保持输出数据直到扫描相关扫描寄存器并将其提供给后续电路块扫描模式，并且在测试操作的测试模式中与外部时钟同步地输出输出数据。

2. 发明授权

US4992845A Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line 失效
标题翻译：具有输入/输出缓冲单元的半导体集成电路器件，每个单元包括排列成一行的多个晶体管区域
公开(公告)号：US4992845A
公开(公告)日：1991-02-12
申请号：US294020
申请日：1989-01-06
申请人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
发明人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
IPC分类号： H01L21/82 , H01L27/118
CPC分类号： H01L27/11898
摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).
摘要翻译：在半导体芯片（1）的中央部分设置有内部逻辑门部（3），设置有用于包围内部逻辑门部（3）的输入/输出缓冲器（4），并且提供接合焊盘（2）在对应于输入/输出缓冲器中的输入/输出缓冲单元（5）的半导体芯片（1）的外围部分中。每个输入/输出缓冲器单元（5）包括输出P-MOS部分（6），输出N-MOS部分（7），输入/逻辑P-MOS部分（8）和输入/ MOS部分（9），它们在从接合焊盘（2）到内部逻辑门部分（3）的方向上分别布置成单行。在上述结构中，键合焊盘（2）的焊盘布置方向上的输入/输出缓冲单元（5）中的每一个的尺寸减小，从而可以根据减少每个输入/输出缓冲单元（5）所需的排列方向的空间的使用。

3. 发明授权

US4870345A Semiconductor intergrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4870345A
公开(公告)日：1989-09-26
申请号：US81095
申请日：1987-08-03
申请人： Ichiro Tomioka , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Takahiko Arakawa
发明人： Ichiro Tomioka , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Takahiko Arakawa
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536
摘要： A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.
摘要翻译：半导体集成电路包括级联异步顺序逻辑电路。在异步时序电路之间提供扫描移位寄存器，以允许将测试数据应用于电路的输入，并根据测试数据锁存和移出由电路提供的输出数据。在扫描移位寄存器和异步顺序电路的输入之间提供附加的选通电路，以防止锁存在扫描移位寄存器中的新数据使测试期间连接到扫描移位寄存器输出的异步时序电路变化。可以使用相同的附加电路来响应于外部产生的门控控制信号来提供受控宽度和/或定时到异步顺序电路输入的脉冲。

4. 发明授权

US4856002A Semiconductor integrated circuit apparatus 失效
标题翻译：半导体集成电路装置
公开(公告)号：US4856002A
公开(公告)日：1989-08-08
申请号：US062439
申请日：1987-06-12
申请人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
发明人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/31816 , G01R31/318533
摘要： A test circuit of a semiconductor integrated circuit apparatus comprising a latch circuit connected to an output terminal of a scan register for holding output data of the scan register stored before scanning in a scan mode during the test operation.
摘要翻译：一种半导体集成电路装置的测试电路，包括连接到扫描寄存器的输出端的锁存电路，用于在测试操作期间以扫描模式保持在扫描之前存储的扫描寄存器的输出数据。

5. 发明授权

US4864579A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4864579A
公开(公告)日：1989-09-05
申请号：US81094
申请日：1987-08-03
申请人： Satoru Kishida , Kazuhiro Sakashita , Ichiro Tomioka
发明人： Satoru Kishida , Kazuhiro Sakashita , Ichiro Tomioka
IPC分类号： G06F11/16 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/318541
摘要： A semiconductor integrated circuit device for transmitting data between a plurality of circuit blocks at least one thereof including a sequential circuit and enabling the circuit blocks to test in a scan testing type which has a plurality of scan registers provided between the plurality of circuit blocks corresponding to the number of bits of data to be transmitted for outputting the output data of the previous stage circuit block as it is at ordinary operating time and for holding and outputting the output data of the previous circuit block or test data for scan test synchronously with an external clock at testing time so that the circuits are connected by a shift register pass in such a manner that the entirety has one shaft register function, and a latch circuit provided at its data input terminal to the data output terminal of the corresponding scan register for outputtting the output data of the corresponding scan register as it is to the circuit block of next stage at ordinary operation time and holding the output data of the corresponding scan register before the scanning operation in a scan mode at testing time to continuously apply the data to the circuit block of next stage and holding and outputting the output data of the corresponding scan register in a test mode synchronously with the external clock, test data setting means for setting serial data of test from the exterior of the circuit device to each of the scan registers, test result outputting means for sequentially outputting the data of each scan register as serial data out of the circuit device, and operation switching means for switching the ordinary operation and the testing operation and switching the scan mode and the test mode, thereby enabling the semiconductor integrated circuit device to be readily subjected to a scan test together with circuit blocks including asynchronous sequential circuits.
摘要翻译：一种半导体集成电路装置，用于在多个电路块之间传输数据，其中至少一个电路块包括时序电路，并使电路块能够以扫描测试类型进行测试，该扫描测试类型具有多个扫描寄存器，该扫描寄存器设置在与要发送的数据的比特数，用于在正常操作时间输出前一级电路块的输出数据，并且用于保持和输出前一个电路块的输出数据或与外部的同步的扫描测试的测试数据时钟，使得电路通过移位寄存器通过连接，使得整体具有一个轴寄存器功能，以及锁存电路，在其数据输入端提供到相应扫描寄存器的数据输出端，用于输出相应的扫描寄存器的输出数据与普通操作下一级的电路块相同并且在测试时间内以扫描模式扫描操作之前保持相应扫描寄存器的输出数据，以将数据连续地施加到下一级的电路块，并在测试中保存和输出相应的扫描寄存器的输出数据与外部时钟同步的模式的测试数据设置装置，用于将测试的串行数据从电路设备的外部设置到每个扫描寄存器;测试结果输出装置，用于将每个扫描寄存器的数据顺序地输出为电路装置和用于切换普通操作和测试操作以及切换扫描模式和测试模式的操作切换装置，从而使得半导体集成电路器件能够容易地与包括异步时序电路的电路块一起进行扫描测试。

6. 发明授权

US4995039A Circuit for transparent scan path testing of integrated circuit devices 失效
标题翻译：集成电路器件透明扫描路径测试电路
公开(公告)号：US4995039A
公开(公告)日：1991-02-19
申请号：US247289
申请日：1988-09-22
申请人： Kazuhiro Sakashita , Ichiro Tomioka , Takeshi Hashizume
发明人： Kazuhiro Sakashita , Ichiro Tomioka , Takeshi Hashizume
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/66
CPC分类号： G01R31/318552
摘要： In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.
摘要翻译：在用于测试集成电路器件的电路中，扫描寄存器（8差分16）和数据选择电路（20-28）根据数据的位数连接在多个电路块（29差分31）之间，扫描寄存器通过移位寄存器路径彼此连接，从而整体上具有一个移位寄存器的功能。寄存器选择电路（20差分28）连接到扫描寄存器的时钟输入端（T1，T2）。除了与要测试的逻辑电路块相对应的扫描寄存器之外的扫描寄存器由寄存器选择电路选择。因此，消除了除所需电路块之前和之后提供的扫描寄存器之外的扫描寄存器的时钟，从而可以减少扫描测试所需的时间。

7. 发明授权

US5911039A Integrated circuit device comprising a plurality of functional modules each performing predetermined function 失效
标题翻译：集成电路装置，包括各自执行预定功能的多个功能模块
公开(公告)号：US5911039A
公开(公告)日：1999-06-08
申请号：US787333
申请日：1997-01-27
申请人： Takeshi Hashizume , Kazuhiro Sakashita
发明人： Takeshi Hashizume , Kazuhiro Sakashita
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G06F11/267 , G06F11/27
CPC分类号： G01R31/318558
摘要： An integrated circuit device is structured by a plurality of functional modules (2a, 2b) each performing a predetermined function, each functional module including a test circuit (3) for testing the corresponding module. Each test circuit comprises a scan path (3a-3d) for receiving test data from a single common input line to perform a test and outputting a test output, a tri-state buffer (4a) for controlling an output of the test output from the scan path to a single common output line, and a scan path selecting circuit (5a) for selectively driving the tri-state buffer. All the selecting circuits in the integrated circuit device are connected in series to constitute as a whole a shift register. A selecting signal of the serial data is inputted to the shift register, so that the test output of each scan path is selectively supplied to the common output line.
摘要翻译：集成电路装置由各自执行预定功能的多个功能模块（2a，2b）构成，每个功能模块包括用于测试相应模块的测试电路（3）。每个测试电路包括用于从单个公共输入线接收测试数据以执行测试并输出测试输出的扫描路径（3a-3d），用于控制测试输出的输出的三态缓冲器（4a）扫描路径到单个公共输出线，以及扫描路径选择电路（5a），用于选择性地驱动三态缓冲器。集成电路装置中的所有选择电路串联连接构成移位寄存器。将串行数据的选择信号输入到移位寄存器，使得每个扫描路径的测试输出被选择性地提供给公共输出线。

8. 发明授权

US5142490A Multiplication circuit with storing means 失效
标题翻译：具有存储装置的乘法电路
公开(公告)号：US5142490A
公开(公告)日：1992-08-25
申请号：US617440
申请日：1990-11-19
申请人： Yoshiki Tsujihashi , Kazuhiro Sakashita
发明人： Yoshiki Tsujihashi , Kazuhiro Sakashita
IPC分类号： G06F7/533 , G06F7/508 , G06F7/52 , G06F7/527 , G06F7/53
CPC分类号： G06F7/5312 , G06F2207/3884
摘要： The multiplication circuit is formed in such a manner that the intermediate sums of partial products are divided into a lower places group and a higher places group and the operations for obtaining the products of the lower places group alone of the intermediate sums already found are carried out parallel to the processing for obtaining the higher places group of the intermediate sums to obtain the higher products thereafter, noting to the fact that the intermediate sums of partial products are found sequentially from lower places to higher places. By adopting such an arrangement, the operations for obtaining the higher places group of the intermediate sums can be processed in parallel with the operations for obtaining the products of the lower places group of the intermediate sums already found, and the higher products are found thereafter. Therefore, the time required for the former-stage processing and that required for the latter-stage processing can be made more uniform.
摘要翻译：乘法电路形成为使得部分乘积的中间和被分成较低的位置组和较高的位置组，并且仅执行已经找到的中间和的单个下位组的乘积的操作平行于获得中间金额的较高地区组的处理以获得其后的较高产品，注意到从较低的地方到更高的地方依次找到部分产品的中间数量的事实。通过这样的安排，可以与获得已经找到的中间数量的下位组的产品的操作并行地获得用于获得中间数额的较高地方组的操作，并且之后发现较高的产品。因此，可以使后期处理所需的时间和后期处理所需的时间更均匀。

9. 发明授权

US4644500A Semiconductor memory device with a controlled precharging arrangement 失效
标题翻译：具有受控预充电布置的半导体存储器件
公开(公告)号：US4644500A
公开(公告)日：1987-02-17
申请号：US638677
申请日：1984-08-08
申请人： Ryo Yonezu , Kazuhiro Sakashita
发明人： Ryo Yonezu , Kazuhiro Sakashita
IPC分类号： G11C11/417 , G11C7/12 , G11C11/41 , G11C11/412 , G11C11/419 , H01L27/10 , G11C13/00
CPC分类号： G11C11/412 , G11C11/419 , G11C7/12
摘要： A semiconductor memory device includes: a memory cell constituted by MOSFETs; a bit line for transmitting a writing and a reading information to or from the memory cell therethrough; a writing-in control signal line for controlling the writing operation onto the memory cell; a first conductive type MOSFET with a source thereof being connected to a power supply terminal, with a gate thereof being connected to the writing-in control signal line, and with a drain thereof being connected to the bit line; the first conductive type MOSFET being adapted to charge up the bit line when no writing is performed in the memory cell; a second conductive type MOSFET with first control line thereof being connected to the bit line, with a gate thereof being connected to the writing-in control signal line, and with a second control line thereof being connected to the output terminal of the writing circuit; and the second conductive type MOSFET being adapted to transmit to the bit line an output from the writing circuit.
摘要翻译：半导体存储器件包括：由MOSFET构成的存储单元; 用于通过其向存储器单元发送写入和读取信息的位线; 写入控制信号线，用于控制对存储单元的写入操作; 第一导电型MOSFET，其源极连接到电源端子，其栅极连接到写入控制信号线，并且其漏极连接到位线; 所述第一导电型MOSFET适于在所述存储单元中不执行写入时对所述位线进行充电; 第二导电型MOSFET，其第一控制线连接到位线，其栅极连接到写入控制信号线，并且其第二控制线连接到写入电路的输出端; 并且所述第二导电型MOSFET适于向所述位线传输来自所述写入电路的输出。

10. 发明授权

US6032246A Bit-slice processing unit having M CPU's reading an N-bit width data element stored bit-sliced across M memories 失效
标题翻译：位片处理单元，其具有M个CPU读取在M个存储器中位分片存储的N位宽数据元素
公开(公告)号：US6032246A
公开(公告)日：2000-02-29
申请号：US45863
申请日：1998-03-23
申请人： Kazuhiro Sakashita
发明人： Kazuhiro Sakashita
IPC分类号： G06F9/38 , G06F15/80 , G06F9/00
CPC分类号： G06F15/8007
摘要： An object is to compatibly improve processing speed and storage capacity of semiconductor memory that the operation portion can use. Each of units (10a, 10b) each having an operation portion (11) and a memory portion (12) is formed of a single semiconductor chip. A data signal is separately stored in the two memory portions (12) in a bit-sliced form and each of the two operation portions (11) can use the 32-bit-wide data signal stored in the entirety of the two memory portions (12) through interconnections (22, 23). That is to say, each operation portion (11) can use a storage capacity twice larger than the capacity that can be ensured in a single semiconductor chip. Provided as interconnections for coupling the semiconductor chips are only the interconnections (22, 23) for transferring data signals from the two memory portions to the two operation portions (11). Hence, the bit width of the interconnections (22, 23) can be increased to increase the transmission speed of the data signals and to increase the processing speed of the device.
摘要翻译：目的是兼容地提高操作部可以使用的半导体存储器的处理速度和存储容量。每个具有操作部分（11）和存储部分（12）的单元（10a，10b）由单个半导体芯片形成。数据信号以位分片形式分别存储在两个存储器部分（12）中，并且两个操作部分（11）中的每一个可以使用存储在两个存储器部分的整体中的32位宽数据信号 12）通过互连（22,23）。也就是说，每个操作部分（11）可以使用比在单个半导体芯片中可以确保的容量大两倍的存储容量。提供用于耦合半导体芯片的互连仅用于将数据信号从两个存储器部分传送到两个操作部分（11）的互连（22,23）。因此，可以增加互连（22,23）的位宽度，以增加数据信号的传输速度并增加设备的处理速度。

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