专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06831331B2 Power MOS transistor for absorbing surge current 失效
标题翻译：功率MOS晶体管，用于吸收浪涌电流
公开(公告)号：US06831331B2
公开(公告)日：2004-12-14
申请号：US09945621
申请日：2001-09-05
申请人： Yasuhiro Kitamura , Toshio Sakakibara , Kenji Kohno , Shoji Mizuno , Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
发明人： Yasuhiro Kitamura , Toshio Sakakibara , Kenji Kohno , Shoji Mizuno , Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0251 , H01L27/0623 , H01L27/085 , H01L29/1087 , H01L29/66674 , H01L29/7395 , H01L29/7801 , H01L29/7824 , H01L29/7835
摘要： A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.
摘要翻译：提供具有功率晶体管结构的半导体器件。功率晶体管结构包括独立地设置在半导体层的表面部分处的多个第一阱; 深部区域，其具有设置在所述第一阱之间的所述半导体层中的部分; 漏电极，连接到所述第一阱中的相应的漏极区; 源电极，其连接到第一阱中的各个源极区域和沟道阱区域，使得漏极电极或源极电极连接到感性负载; 以及连接构件，用于向深区域提供源极电位，其中当漏电极连接到感性负载时，连接构件可配置为连接到漏电极，并且当源电极连接到源电极时连接到源电极表示感性负载。

2. 发明授权

US6104076A Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US6104076A
公开(公告)日：2000-08-15
申请号：US748896
申请日：1996-11-15
申请人： Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
发明人： Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
IPC分类号： H01L21/336 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/085 , H01L29/739 , H01L29/78 , H01L29/76 , H01L23/58
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0251 , H01L27/0623 , H01L27/085 , H01L29/063 , H01L29/1083 , H01L29/1095 , H01L29/66674 , H01L29/7395 , H01L29/7801 , H01L29/7824 , H01L29/7835
摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

3. 发明授权

US06242787B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06242787B1
公开(公告)日：2001-06-05
申请号：US08748896
申请日：1996-11-15
申请人： Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
发明人： Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0251 , H01L27/0623 , H01L27/085 , H01L29/063 , H01L29/1083 , H01L29/1095 , H01L29/66674 , H01L29/7395 , H01L29/7801 , H01L29/7824 , H01L29/7835
摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.
摘要翻译：一种包括减小表面场强度型LDMOS晶体管的半导体器件，其可以防止当向其漏极施加反向电压时在沟道形成部分处的元件的击穿。在N型衬底中形成P阱和N阱以产生双阱结构，其中源极被设置为与N型衬底的电位相等。 N阱的漂移区域具有掺杂浓度以满足所谓的RESURF条件，其可以提供高的击穿电压低导通电阻。当向漏极施加反向电压时，包括N阱，P阱和N型衬底的寄生双极晶体管形成朝向衬底的通电路径，使得元件在沟道形成时击穿在施加反向电压时部分是可避免的。

4. 发明授权

US6104078A Design for a semiconductor device having elements isolated by insulating regions 失效
标题翻译：设计具有通过绝缘区隔离的元件的半导体器件
公开(公告)号：US6104078A
公开(公告)日：2000-08-15
申请号：US941756
申请日：1997-09-30
申请人： Makio Iida , Mitsuhiro Saitou , Akitaka Murata , Hiroyuki Ban , Tadashi Suzuki , Toshio Sakakibara , Takayuki Sugisaka , Shoji Miura
发明人： Makio Iida , Mitsuhiro Saitou , Akitaka Murata , Hiroyuki Ban , Tadashi Suzuki , Toshio Sakakibara , Takayuki Sugisaka , Shoji Miura
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76264
摘要： A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.
摘要翻译：一种半导体器件，包括具有主表面的半导体衬底。绝缘膜形成在半导体衬底的主表面上。半导体层被放置在绝缘膜上。从半导体层的表面延伸到绝缘膜的侧绝缘区域将半导体层分成元件区域。元件区域通过侧绝缘区域和绝缘膜彼此隔离。半导体基板的电阻率为1.5欧姆·厘米或更低。将半导体衬底处的电压设定为给定电压。

5. 发明授权

US06287933B1 Semiconductor device having thin film resistor and method of producing same 失效
标题翻译：具有薄膜电阻器的半导体器件及其制造方法
公开(公告)号：US06287933B1
公开(公告)日：2001-09-11
申请号：US08015268
申请日：1992-01-03
申请人： Makio Iida , Shoji Miura , Kanemitsu Terada , Hiroyuki Ban , Kiyoshi Yamamoto , Katsuyoshi Oda , Yoshihiko Isobe
发明人： Makio Iida , Shoji Miura , Kanemitsu Terada , Hiroyuki Ban , Kiyoshi Yamamoto , Katsuyoshi Oda , Yoshihiko Isobe
IPC分类号： H01L2120
CPC分类号： H01L28/24
摘要： A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.
摘要翻译：一种具有薄膜电阻器的半导体器件，该薄膜电阻器至少包含铬，硅和氮，并且形成在具有特定比例的化学成分的基板上，该半导体器件具有使其由于温度导致的电阻值的变化的特性可以有效地抑制变化。

6. 发明授权

US06034556A Sample-and-hold circuit including operational amplifier as an input circuit 失效
标题翻译：采样保持电路包括运算放大器作为输入电路
公开(公告)号：US06034556A
公开(公告)日：2000-03-07
申请号：US19363
申请日：1998-02-05
申请人： Takahisa Koyasu , Mitsuhiro Saitou , Hiroyuki Ban
发明人： Takahisa Koyasu , Mitsuhiro Saitou , Hiroyuki Ban
IPC分类号： G11C27/02 , H03F3/30 , H03F3/45
CPC分类号： H03F3/3071 , G11C27/026 , H03F3/45085 , H03F2203/45594 , H03F2203/45612 , H03F2203/45618 , H03F2203/45674 , H03F2203/45722
摘要： An operational amplifier charges a charge storage capacitor in response to an input signal supplied to a non-inverting input terminal. When a switching signal is low, NPN transistors disposed in an output open circuit are on. Therefore, output transistors disposed in a push-pull circuit are off and the output signal is cut off. Further, in this situation, the potential of a phase compensation capacitor is held because AC coupling of the phase compensation capacitor does not occur.
摘要翻译：响应于提供给非反相输入端的输入信号，运算放大器对电荷存储电容器充电。当开关信号为低电平时，设置在输出开路中的NPN晶体管导通。因此，设置在推挽电路中的输出晶体管截止，输出信号被切断。此外，在这种情况下，由于不发生相位补偿电容器的AC耦合，因此保持相位补偿电容器的电位。

7. 发明授权

US5739546A Semiconductor wafer 失效
标题翻译：半导体晶圆
公开(公告)号：US5739546A
公开(公告)日：1998-04-14
申请号：US666646
申请日：1996-06-18
申请人： Mitsuhiro Saitou , Kouji Numazaki , Hiroyuki Ban
发明人： Mitsuhiro Saitou , Kouji Numazaki , Hiroyuki Ban
IPC分类号： H01L21/66 , H01L21/822 , H01L23/528 , H01L23/58 , H01L27/02 , H01L27/04 , H01L27/10
CPC分类号： H01L22/32 , H01L23/5286 , H01L27/0218 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor wafer, having a relatively wide power supply line and ground line, and which can also prevent short-circuiting between these lines. Multiple integrated circuit formation regions, whereon integrated circuits have been formed, are disposed on a semiconductor wafer. A silicon oxide film is formed on a silicon substrate, and a ground line conductor is formed on the silicon oxide film. This ground line conductor is extended over scribe lines. A layer insulation film composed of silicon oxide film is deposited on the silicon oxide film with the ground line conductor interposed therebetween, and a power supply line conductor is formed on the layer insulation film to overlap the ground line conductor. The power supply line conductor is extended over scribe lines. In the integrated circuit formation regions, a power supply pad and the power supply line conductor are electrically connected. A ground pad and the ground line conductor are also electrically connected.
摘要翻译：具有相对宽的电源线和接地线的半导体晶片，并且还可以防止这些线之间的短路。多个集成电路形成区域已经形成集成电路，被布置在半导体晶片上。在硅衬底上形成氧化硅膜，在氧化硅膜上形成接地线导体。该接地线导体在划线上延伸。在氧化硅膜上沉积由氧化硅膜构成的层绝缘膜，其间插入有接地线导体，并且在该层绝缘膜上形成与该接地线导体重叠的电源线导体。电源线导体在划线上延伸。在集成电路形成区域中，电源焊盘和电源线导体电连接。接地焊盘和接地线导体也电连接。

8. 发明授权

US6081040A Semiconductor device having alignment mark 失效
标题翻译：具有对准标记的半导体器件
公开(公告)号：US6081040A
公开(公告)日：2000-06-27
申请号：US39340
申请日：1998-03-16
申请人： Shoichi Okuda , Mitsuhiro Saitou , Hiroyuki Ban
发明人： Shoichi Okuda , Mitsuhiro Saitou , Hiroyuki Ban
IPC分类号： H01L27/04 , H01L21/822 , H01L23/544 , H01L21/465
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002
摘要： An alignment mark for determining a position of a thin film resistor formed on a semiconductor chip. The alignment mark is disposed on a capacitor formation region of the semiconductor chip. Because aluminum wiring members of the semiconductor chip are not disposed adjacent to the alignment mark within the capacitor formation region, the alignment mark can be precisely recognized. As a result, the position of the thin film resistor can be also precisely determined.
摘要翻译：用于确定形成在半导体芯片上的薄膜电阻器的位置的对准标记。对准标记设置在半导体芯片的电容器形成区域上。由于半导体芯片的铝布线构件不与电容器形成区域内的对准标记相邻配置，因此可以精确地识别对准标记。结果，也可以精确地确定薄膜电阻器的位置。

9. 发明授权

US6157246A Load driving circuit with boosting timing control 失效
标题翻译：负载驱动电路具有升压时序控制
公开(公告)号：US6157246A
公开(公告)日：2000-12-05
申请号：US109732
申请日：1998-07-02
申请人： Mitsuhiro Saitou , Hiroyuki Ban
发明人： Mitsuhiro Saitou , Hiroyuki Ban
IPC分类号： B60R21/01 , G05F1/10
CPC分类号： B60R21/017
摘要： The present invention is aimed at avoiding noise generation accompanying switching actions in booster circuits for a load such as an air-bag driving circuit. In an air-bag driving circuit, which is designed to actuate an igniting transistor 13 in response to output of a collision detecting signal from a collision detector 7 for detecting a collision condition of a vehicle so as to supply an igniting current to a squib 11 based on a voltage boosted by booster circuits 4 and 5, the boosting operation of the booster circuits 4 and 5 is inhibited while the collision detecting signal is absent and started when the collision detecting signal is output from the collision detector 7.
摘要翻译：本发明旨在避免伴随诸如气囊驱动电路的负载的升压电路中的切换动作的噪声产生。在气囊驱动电路中，其被设计成响应来自碰撞检测器7的碰撞检测信号的输出来致动点火晶体管13，用于检测车辆的碰撞状况，以便向点火器11提供点火电流基于由升压电路4和5升压的电压，当碰撞检测信号从碰撞检测器7输出时，不存在冲突检测信号并开始升压电路4和5的升压操作。

10. 发明授权

US5719522A Reference voltage generating circuit having reduced current consumption with varying loads 失效
标题翻译：参考电压发生电路具有随着负载变化而具有降低的电流消耗
公开(公告)号：US5719522A
公开(公告)日：1998-02-17
申请号：US814935
申请日：1997-03-12
申请人： Mitsuhiro Saitou , Hajime Ito , Kiyoshi Yamamoto , Hiroyuki Ban
发明人： Mitsuhiro Saitou , Hajime Ito , Kiyoshi Yamamoto , Hiroyuki Ban
IPC分类号： G05F3/30 , G05F3/22 , G06F1/26 , G11C5/14 , G05F1/10
CPC分类号： G05F3/222 , G11C5/147
摘要： A variable load current supply unit supplies a current to be consumed by a constant voltage output unit to a power source terminal thereof, and supplies a current to be consumed by a load circuit thereto through a reference voltage output terminal. The constant voltage output unit maintains a potential of the power source terminal thereof, i.e., a potential of the reference voltage output terminal, at a fixed potential. A base potential control unit negatively feeds back changes in the potential on the reference voltage output terminal to a base of an emitter follower transistor in the variable load current supply unit. In this way, when the current consumed by the load current is reduced and the potential on the reference voltage output terminal thereby slightly increases the current supplied by the variable load current supply unit decreases.
摘要翻译：可变负载电流供给单元将恒定电压输出单元消耗的电流供给到其电源端子，并通过基准电压输出端子向负载电路供给要消耗的电流。恒定电压输出单元将电源端子的电位即基准电压输出端子的电位维持在固定电位。基极电位控制单元将可变负载电流供给单元中的基准电压输出端子上的电位的变化负反馈到射极跟随器晶体管的基极。以这种方式，当负载电流消耗的电流减小并且参考电压输出端子上的电位稍微增加时，可变负载电流供应单元提供的电流减小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式