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1. 发明授权

US07864588B2 Minimizing read disturb in an array flash cell 有权
标题翻译：最小化阵列闪存单元中的读取干扰
公开(公告)号：US07864588B2
公开(公告)日：2011-01-04
申请号：US12232418
申请日：2008-09-17
申请人： Yoram Betser , Yair Sofer , Oren Shlomo , Avri Harush
发明人： Yoram Betser , Yair Sofer , Oren Shlomo , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28 , G11C16/3427
摘要： A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.
摘要翻译：一种通过使用第一漏极电压来读取阵列单元并使用第二较低漏极电压来读取参考单元的方法来减小NVM单元中的读取干扰。阵列和参考单元的全局位线（GBL）上的漏极电压可能彼此基本相同，以保持主路径电容匹配，而参考单元的局部位线（LBL）上的漏极电压可能低于漏极本地位线上的电压（LBL）用于阵列单元以减少第二位效应。可以使用夹紧装置或降压装置来降低其排出口处的参考单元的漏极电压。

2. 发明申请

US20090073760A1 Minimizing read disturb in an array flash cell 有权
标题翻译：最小化阵列闪存单元中的读取干扰
公开(公告)号：US20090073760A1
公开(公告)日：2009-03-19
申请号：US12232418
申请日：2008-09-17
申请人： Yoram Betser , Yair Sofer , Oren Shlomo , Avri Harush
发明人： Yoram Betser , Yair Sofer , Oren Shlomo , Avri Harush
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28 , G11C16/3427
摘要： A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.
摘要翻译：一种通过使用第一漏极电压来读取阵列单元并使用第二较低漏极电压来读取参考单元的方法来减小NVM单元中的读取干扰。阵列和参考单元的全局位线（GBL）上的漏极电压可能彼此基本相同，以保持主路径电容匹配，而参考单元的局部位线（LBL）上的漏极电压可能低于漏极本地位线上的电压（LBL）用于阵列单元以减少第二位效应。可以使用夹紧装置或降压装置来降低其排出口处的参考单元的漏极电压。

3. 发明授权

US08098525B2 Pre-charge sensing scheme for non-volatile memory (NVM) 有权
标题翻译：用于非易失性存储器（NVM）的预充电感测方案
公开(公告)号：US08098525B2
公开(公告)日：2012-01-17
申请号：US12232437
申请日：2008-09-17
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

4. 发明申请

US20120063238A1 PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM) 有权
标题翻译：非易失性存储器（NVM）的预充电传感方案
公开(公告)号：US20120063238A1
公开(公告)日：2012-03-15
申请号：US13301826
申请日：2011-11-22
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

5. 发明申请

US20090073774A1 Pre-charge sensing scheme for non-volatile memory (NVM) 有权
标题翻译：用于非易失性存储器（NVM）的预充电感测方案
公开(公告)号：US20090073774A1
公开(公告)日：2009-03-19
申请号：US12232437
申请日：2008-09-17
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。可以根据每个地址的预定义表来选择预充电的全局位线。可以根据在下一个读取周期期间这些全局位线是否会干扰管道来完成全局位线的选择。

6. 发明授权

US08593881B2 Pre-charge sensing scheme for non-volatile memory (NVM) 有权
标题翻译：用于非易失性存储器（NVM）的预充电感测方案
公开(公告)号：US08593881B2
公开(公告)日：2013-11-26
申请号：US13301826
申请日：2011-11-22
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

7. 发明授权

US07466594B2 Dynamic matching of signal path and reference path for sensing 有权
标题翻译：信号路径和参考路径的动态匹配用于感测
公开(公告)号：US07466594B2
公开(公告)日：2008-12-16
申请号：US11490539
申请日：2006-07-19
申请人： Yair Sofer , Eduardo Maayan , Yoram Betser
发明人： Yair Sofer , Eduardo Maayan , Yoram Betser
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/14 , G11C16/0491
摘要： A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
摘要翻译：一种用于操作非易失性存储单元器件的方法，所述方法包括提供连接到字线和局部位线的存储器阵列单元的阵列，所述局部位线经由选择晶体管连接到全局位线，所述阵列被分成隔离扇区，提供一个感测放大器，可操作以经由感测路径感测存储器阵列单元，该感测路径包括至少一个本地位线，至少一个选择晶体管，至少一个访问的全局位线和YMUX，提供参考单元位于参考微型阵列中，参考单元连接到YMUX并且经由另一感测路径连接到读出放大器，利用公共位线（BL）驱动器驱动存储器阵列单元和参考单元通过访问的全局位线经由YMUX连接到存储器阵列单元和参考单元，并且匹配存储器阵列单元的感测路径和参考cel的感测路径通过在参考单元和读出放大器之间的感测路径中使用非访问的全局位线，将其传送到读出放大器。可以动态地选择非访问的全局位线作为与用于驱动阵列的排水管和参考单元的全局位线相邻的全局位线。

8. 发明授权

US07190212B2 Power-up and BGREF circuitry 有权
标题翻译：上电和BGREF电路
公开(公告)号：US07190212B2
公开(公告)日：2007-03-13
申请号：US10862401
申请日：2004-06-08
申请人： Joseph S. Shor , Yoram Betser , Yair Sofer
发明人： Joseph S. Shor , Yoram Betser , Yair Sofer
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.
摘要翻译：电路包括具有将电阻分压电源电压与至少两个工艺参数电压的功能进行比较的多个MOS晶体管的BGREF（带隙电压基准）比较器。

9. 发明申请

US20060146624A1 Current folding sense amplifier 审中-公开
标题翻译：电流折叠放大器
公开(公告)号：US20060146624A1
公开(公告)日：2006-07-06
申请号：US11291302
申请日：2005-12-01
申请人： Yoram Betser , Yair Sofer
发明人： Yoram Betser , Yair Sofer
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C16/0491
摘要： A method for sensing logical content stored in a memory cell, the method including inputting an input cell current of a selected array cell of a memory array to an input stage, and folding the input cell current and using it to discharge an input of a latch, the latch providing an output digital signal indicative of a logical content stored in the selected array cell.
摘要翻译：一种用于感测存储在存储单元中的逻辑内容的方法，所述方法包括将存储器阵列的选定的阵列单元的输入单元电流输入到输入级，并且折叠输入单元电流并使用该单元电流来对锁存器的输入进行放电，所述锁存器提供指示存储在所选择的阵列单元中的逻辑内容的输出数字信号。

10. 发明申请

US20060285408A1 METHOD CIRCUIT AND SYSTEM FOR COMPENSATING FOR TEMPERATURE INDUCED MARGIN LOSS IN NON-VOLATILE MEMORY CELLS 有权
标题翻译：用于补偿非挥发性记忆细胞中温度诱导的损伤的方法电路和系统
公开(公告)号：US20060285408A1
公开(公告)日：2006-12-21
申请号：US11155252
申请日：2005-06-17
申请人： Yoram Betser , Yair Sofer , Eduardo Maayan
发明人： Yoram Betser , Yair Sofer , Eduardo Maayan
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/3445 , G11C16/3459
摘要： The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading. The pool of reference cells may consist of Program verify reference cells, or Erase verify reference cells.
摘要翻译：本发明包括用于在非易失性存储器（“NVM”）单元中随时间和超过工作温度范围补偿余量损失的方法和系统，该方法包括基于获得的温度读数来选择参考水平从直接或间接热耦合到NVM单元的温度感测元件。参考电平可以从由各种类型的参考电平组成的组中选择，或者可以通过基于温度读数调整单个参考的输出来获得，或者可以通过利用预先存储的转换数据，该转换数据将给定的温度读数与相应的温度范围相关联，所述对应的温度范围又与相应的参考水平相关联。可以提供同样参考单元的池，并且可以基于其与温度读数的关联从该池中选择参考水平。参考单元池可以由程序验证参考单元或擦除验证参考单元组成。

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