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1. 发明授权

US07466594B2 Dynamic matching of signal path and reference path for sensing 有权
标题翻译：信号路径和参考路径的动态匹配用于感测
公开(公告)号：US07466594B2
公开(公告)日：2008-12-16
申请号：US11490539
申请日：2006-07-19
申请人： Yair Sofer , Eduardo Maayan , Yoram Betser
发明人： Yair Sofer , Eduardo Maayan , Yoram Betser
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/14 , G11C16/0491
摘要： A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
摘要翻译：一种用于操作非易失性存储单元器件的方法，所述方法包括提供连接到字线和局部位线的存储器阵列单元的阵列，所述局部位线经由选择晶体管连接到全局位线，所述阵列被分成隔离扇区，提供一个感测放大器，可操作以经由感测路径感测存储器阵列单元，该感测路径包括至少一个本地位线，至少一个选择晶体管，至少一个访问的全局位线和YMUX，提供参考单元位于参考微型阵列中，参考单元连接到YMUX并且经由另一感测路径连接到读出放大器，利用公共位线（BL）驱动器驱动存储器阵列单元和参考单元通过访问的全局位线经由YMUX连接到存储器阵列单元和参考单元，并且匹配存储器阵列单元的感测路径和参考cel的感测路径通过在参考单元和读出放大器之间的感测路径中使用非访问的全局位线，将其传送到读出放大器。可以动态地选择非访问的全局位线作为与用于驱动阵列的排水管和参考单元的全局位线相邻的全局位线。

2. 发明授权

US07190212B2 Power-up and BGREF circuitry 有权
标题翻译：上电和BGREF电路
公开(公告)号：US07190212B2
公开(公告)日：2007-03-13
申请号：US10862401
申请日：2004-06-08
申请人： Joseph S. Shor , Yoram Betser , Yair Sofer
发明人： Joseph S. Shor , Yoram Betser , Yair Sofer
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.
摘要翻译：电路包括具有将电阻分压电源电压与至少两个工艺参数电压的功能进行比较的多个MOS晶体管的BGREF（带隙电压基准）比较器。

3. 发明申请

US20060146624A1 Current folding sense amplifier 审中-公开
标题翻译：电流折叠放大器
公开(公告)号：US20060146624A1
公开(公告)日：2006-07-06
申请号：US11291302
申请日：2005-12-01
申请人： Yoram Betser , Yair Sofer
发明人： Yoram Betser , Yair Sofer
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C16/0491
摘要： A method for sensing logical content stored in a memory cell, the method including inputting an input cell current of a selected array cell of a memory array to an input stage, and folding the input cell current and using it to discharge an input of a latch, the latch providing an output digital signal indicative of a logical content stored in the selected array cell.
摘要翻译：一种用于感测存储在存储单元中的逻辑内容的方法，所述方法包括将存储器阵列的选定的阵列单元的输入单元电流输入到输入级，并且折叠输入单元电流并使用该单元电流来对锁存器的输入进行放电，所述锁存器提供指示存储在所选择的阵列单元中的逻辑内容的输出数字信号。

4. 发明申请

US20050269619A1 MOS capacitor with reduced parasitic capacitance 有权
标题翻译：具有降低的寄生电容的MOS电容
公开(公告)号：US20050269619A1
公开(公告)日：2005-12-08
申请号：US10862405
申请日：2004-06-08
申请人： Joseph Shor , Eduardo Maayan , Yoram Betser
发明人： Joseph Shor , Eduardo Maayan , Yoram Betser
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L29/94 , H01L27/108
CPC分类号： H01L27/0811
摘要： A capacitor including a first active layer capacitively coupled to a second active layer, the second active layer being capacitively coupled to a third layer, the third layer being capacitively coupled to a fourth layer, wherein an anode of the capacitor is connected to one of the first and second active layers, and a cathode of the capacitor is connected to the other one of the first and second active layers, and wherein the third layer is left floating. The fourth layer may be connected to a supply voltage, such as but not limited to, ground.
摘要翻译：一种电容器，包括电容耦合到第二有源层的第一有源层，所述第二有源层电容耦合到第三层，所述第三层电容耦合到第四层，其中所述电容器的阳极连接到第一和第二有源层，并且电容器的阴极连接到第一和第二有源层中的另一个，并且其中第三层是浮置的。第四层可以连接到电源电压，例如但不限于接地。

5. 发明授权

US08098525B2 Pre-charge sensing scheme for non-volatile memory (NVM) 有权
标题翻译：用于非易失性存储器（NVM）的预充电感测方案
公开(公告)号：US08098525B2
公开(公告)日：2012-01-17
申请号：US12232437
申请日：2008-09-17
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

6. 发明申请

US20080239599A1 Clamping Voltage Events Such As ESD 审中-公开
标题翻译：钳位电压事件如ESD
公开(公告)号：US20080239599A1
公开(公告)日：2008-10-02
申请号：US11695029
申请日：2007-04-01
申请人： Yehuda Yizraeli , Yoram Betser , Ilan Bloom
发明人： Yehuda Yizraeli , Yoram Betser , Ilan Bloom
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H02H3/44
摘要： A clamping scheme using dual sensing detection, which can sense and differentiate (in the extreme) between a high voltage level and fast (enough) slope (indicative of ESD), and low voltage level and slow slope (indicative of normal operation) and/or low voltage level and fast slope (indicative of hot insertion). It can also generate a locking scheme to ensure proper discharging only if the level is above high level and fast slope. It can also operate the clamping for a short time only if the level is below the high level but above the low level, and of sufficient slope.
摘要翻译：使用双重感测检测的钳位方案，其可以在高电压电平和快（足够）的斜率（指示ESD））以及低电压电平和缓慢的斜率（指示正常操作）之间感测和区分（在极端情况下）和/ 或低电压电平和快速斜率（表示热插入）。它也可以产生锁定方案，以确保正常放电只有当水平高于高水平和快速的斜率。只有当电平低于高电平但高于低电平且具有足够的斜率时，它也可以短时间操作钳位。

7. 发明申请

US20060285408A1 METHOD CIRCUIT AND SYSTEM FOR COMPENSATING FOR TEMPERATURE INDUCED MARGIN LOSS IN NON-VOLATILE MEMORY CELLS 有权
标题翻译：用于补偿非挥发性记忆细胞中温度诱导的损伤的方法电路和系统
公开(公告)号：US20060285408A1
公开(公告)日：2006-12-21
申请号：US11155252
申请日：2005-06-17
申请人： Yoram Betser , Yair Sofer , Eduardo Maayan
发明人： Yoram Betser , Yair Sofer , Eduardo Maayan
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/3445 , G11C16/3459
摘要： The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading. The pool of reference cells may consist of Program verify reference cells, or Erase verify reference cells.
摘要翻译：本发明包括用于在非易失性存储器（“NVM”）单元中随时间和超过工作温度范围补偿余量损失的方法和系统，该方法包括基于获得的温度读数来选择参考水平从直接或间接热耦合到NVM单元的温度感测元件。参考电平可以从由各种类型的参考电平组成的组中选择，或者可以通过基于温度读数调整单个参考的输出来获得，或者可以通过利用预先存储的转换数据，该转换数据将给定的温度读数与相应的温度范围相关联，所述对应的温度范围又与相应的参考水平相关联。可以提供同样参考单元的池，并且可以基于其与温度读数的关联从该池中选择参考水平。参考单元池可以由程序验证参考单元或擦除验证参考单元组成。

8. 发明申请

US20050270089A1 Power-up and BGREF circuitry 有权
标题翻译：上电和BGREF电路
公开(公告)号：US20050270089A1
公开(公告)日：2005-12-08
申请号：US10862401
申请日：2004-06-08
申请人： Joseph Shor , Yoram Betser , Yair Sofer
发明人： Joseph Shor , Yoram Betser , Yair Sofer
IPC分类号： G05F1/10 , G05F3/30
CPC分类号： G05F3/30
摘要： Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.
摘要翻译：电路包括具有将电阻分压电源电压与至少两个工艺参数电压的功能进行比较的多个MOS晶体管的BGREF（带隙电压基准）比较器。

9. 发明申请

US20120063238A1 PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM) 有权
标题翻译：非易失性存储器（NVM）的预充电传感方案
公开(公告)号：US20120063238A1
公开(公告)日：2012-03-15
申请号：US13301826
申请日：2011-11-22
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

10. 发明授权

US07532529B2 Apparatus and methods for multi-level sensing in a memory array 有权
标题翻译：用于存储器阵列中多级感测的装置和方法
公开(公告)号：US07532529B2
公开(公告)日：2009-05-12
申请号：US11464253
申请日：2006-08-14
申请人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
发明人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C16/32 , G11C2211/5634
摘要： A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.
摘要翻译：一种用于感测从存储器阵列内的阵列单元接收的信号的方法，所述方法包括以下步骤：产生与所述存储器阵列的所选阵列单元的电流成比例的模拟电压Vddr，以及将所述模拟电压Vddr与参考模拟电压Vcomp以产生输出数字信号。还提供了一种用于通过将来自存储器单元的信号变换为时间延迟来感测存储单元的方法，以及通过将时间延迟与参考单元的时间延迟进行比较来感测存储单元。还公开了相关装置。

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