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1. 发明授权

US07755938B2 Method for reading a memory array with neighbor effect cancellation 有权
标题翻译：读取具有相邻效果消除的存储器阵列的方法
公开(公告)号：US07755938B2
公开(公告)日：2010-07-13
申请号：US10826375
申请日：2004-04-19
申请人： Shahar Atir , Oleg Dadashev , Yair Sofer , Eduardo Maayan
发明人： Shahar Atir , Oleg Dadashev , Yair Sofer , Eduardo Maayan
IPC分类号： G11C16/04
CPC分类号： G11C7/02 , G11C7/06 , G11C7/08 , G11C16/0475 , G11C16/0491 , G11C16/26
摘要： Disclosed is a method of reducing the neighbor effect while reading data in a non-volatile memory array. The method includes sensing adjacent memory cells. The sensing of the two adjacent cells is performed substantially simultaneously and through at least a partially shared sensing path.
摘要翻译：公开了一种在非易失性存储器阵列中读取数据的同时降低相邻效应的方法。该方法包括感测相邻的存储单元。两个相邻小区的感测基本上同时进行，并通过至少部分共享的感测路径进行。

2. 发明申请

US20060285408A1 METHOD CIRCUIT AND SYSTEM FOR COMPENSATING FOR TEMPERATURE INDUCED MARGIN LOSS IN NON-VOLATILE MEMORY CELLS 有权
标题翻译：用于补偿非挥发性记忆细胞中温度诱导的损伤的方法电路和系统
公开(公告)号：US20060285408A1
公开(公告)日：2006-12-21
申请号：US11155252
申请日：2005-06-17
申请人： Yoram Betser , Yair Sofer , Eduardo Maayan
发明人： Yoram Betser , Yair Sofer , Eduardo Maayan
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/3445 , G11C16/3459
摘要： The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading. The pool of reference cells may consist of Program verify reference cells, or Erase verify reference cells.
摘要翻译：本发明包括用于在非易失性存储器（“NVM”）单元中随时间和超过工作温度范围补偿余量损失的方法和系统，该方法包括基于获得的温度读数来选择参考水平从直接或间接热耦合到NVM单元的温度感测元件。参考电平可以从由各种类型的参考电平组成的组中选择，或者可以通过基于温度读数调整单个参考的输出来获得，或者可以通过利用预先存储的转换数据，该转换数据将给定的温度读数与相应的温度范围相关联，所述对应的温度范围又与相应的参考水平相关联。可以提供同样参考单元的池，并且可以基于其与温度读数的关联从该池中选择参考水平。参考单元池可以由程序验证参考单元或擦除验证参考单元组成。

3. 发明申请

US20050270089A1 Power-up and BGREF circuitry 有权
标题翻译：上电和BGREF电路
公开(公告)号：US20050270089A1
公开(公告)日：2005-12-08
申请号：US10862401
申请日：2004-06-08
申请人： Joseph Shor , Yoram Betser , Yair Sofer
发明人： Joseph Shor , Yoram Betser , Yair Sofer
IPC分类号： G05F1/10 , G05F3/30
CPC分类号： G05F3/30
摘要： Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.
摘要翻译：电路包括具有将电阻分压电源电压与至少两个工艺参数电压的功能进行比较的多个MOS晶体管的BGREF（带隙电压基准）比较器。

4. 发明授权

US06577514B2 Charge pump with constant boosted output voltage 失效
标题翻译：电荷泵具有恒定的升压输出电压
公开(公告)号：US06577514B2
公开(公告)日：2003-06-10
申请号：US09827511
申请日：2001-04-05
申请人： Joseph Shor , Yair Sofer , Eduardo Maayan
发明人： Joseph Shor , Yair Sofer , Eduardo Maayan
IPC分类号： H02M318
CPC分类号： H02M3/07
摘要： A charge pump regulator for providing a constant boosted voltage at the output of a charge pump includes: 1) a charge pump; 2) a clamping regulator; and 3) a clamping transistor. Certain preferred embodiments further include an auxiliary charge pump that provides a voltage above VDD or below ground to the clamping regulator. The clamping transistor provides a voltage supply level (Vsupp) to the oscillating clock signal generator which uses Vsupp to drive the oscillating clock signals that charge the energy injection capacitors of the charge pump between Vsupp and a reference voltage (Vref). The invention includes regulators for use with positive and negative charge pumps.
摘要翻译：用于在电荷泵的输出处提供恒定升压电压的电荷泵调节器包括：1）电荷泵; 2）夹紧调节器; 和3）钳位晶体管。某些优选实施例还包括向钳位调节器提供高于VDD或低于地电压的辅助电荷泵。钳位晶体管向振荡时钟信号发生器提供电压电平（Vsupp），其使用Vsupp来驱动在Vsupp和参考电压（Vref）之间对电荷泵的能量注入电容器充电的振荡时钟信号。本发明包括用于正和负电荷泵的调节器。

5. 发明申请

US20090109755A1 Neighbor block refresh for non-volatile memory 审中-公开
标题翻译：非易失性存储器的相邻块刷新
公开(公告)号：US20090109755A1
公开(公告)日：2009-04-30
申请号：US12289289
申请日：2008-10-24
申请人： Mori Edan , Assaf Shappir , Yair Sofer
发明人： Mori Edan , Assaf Shappir , Yair Sofer
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/0475 , G11C16/3418 , G11C16/3431
摘要： Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a sub-population of Vt distributions at a given program level. Various timings and strategies for performing the refresh operation are disclosed. The effects of word line disturb (gate disturb) may thereby be reduced.
摘要翻译：阵列给定物理扇区中的两个或多个擦除扇区（块）。当（之后）擦除目标块时，通过在给定的程序级检查Vt分布的子群来确定是否需要刷新相邻块。公开了用于执行刷新操作的各种定时和策略。因此可以减少字线干扰（门扰动）的影响。

6. 发明授权

US07466594B2 Dynamic matching of signal path and reference path for sensing 有权
标题翻译：信号路径和参考路径的动态匹配用于感测
公开(公告)号：US07466594B2
公开(公告)日：2008-12-16
申请号：US11490539
申请日：2006-07-19
申请人： Yair Sofer , Eduardo Maayan , Yoram Betser
发明人： Yair Sofer , Eduardo Maayan , Yoram Betser
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/14 , G11C16/0491
摘要： A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
摘要翻译：一种用于操作非易失性存储单元器件的方法，所述方法包括提供连接到字线和局部位线的存储器阵列单元的阵列，所述局部位线经由选择晶体管连接到全局位线，所述阵列被分成隔离扇区，提供一个感测放大器，可操作以经由感测路径感测存储器阵列单元，该感测路径包括至少一个本地位线，至少一个选择晶体管，至少一个访问的全局位线和YMUX，提供参考单元位于参考微型阵列中，参考单元连接到YMUX并且经由另一感测路径连接到读出放大器，利用公共位线（BL）驱动器驱动存储器阵列单元和参考单元通过访问的全局位线经由YMUX连接到存储器阵列单元和参考单元，并且匹配存储器阵列单元的感测路径和参考cel的感测路径通过在参考单元和读出放大器之间的感测路径中使用非访问的全局位线，将其传送到读出放大器。可以动态地选择非访问的全局位线作为与用于驱动阵列的排水管和参考单元的全局位线相邻的全局位线。

7. 发明授权

US07190212B2 Power-up and BGREF circuitry 有权
标题翻译：上电和BGREF电路
公开(公告)号：US07190212B2
公开(公告)日：2007-03-13
申请号：US10862401
申请日：2004-06-08
申请人： Joseph S. Shor , Yoram Betser , Yair Sofer
发明人： Joseph S. Shor , Yoram Betser , Yair Sofer
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.
摘要翻译：电路包括具有将电阻分压电源电压与至少两个工艺参数电压的功能进行比较的多个MOS晶体管的BGREF（带隙电压基准）比较器。

8. 发明申请

US20060146624A1 Current folding sense amplifier 审中-公开
标题翻译：电流折叠放大器
公开(公告)号：US20060146624A1
公开(公告)日：2006-07-06
申请号：US11291302
申请日：2005-12-01
申请人： Yoram Betser , Yair Sofer
发明人： Yoram Betser , Yair Sofer
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C16/0491
摘要： A method for sensing logical content stored in a memory cell, the method including inputting an input cell current of a selected array cell of a memory array to an input stage, and folding the input cell current and using it to discharge an input of a latch, the latch providing an output digital signal indicative of a logical content stored in the selected array cell.
摘要翻译：一种用于感测存储在存储单元中的逻辑内容的方法，所述方法包括将存储器阵列的选定的阵列单元的输入单元电流输入到输入级，并且折叠输入单元电流并使用该单元电流来对锁存器的输入进行放电，所述锁存器提供指示存储在所选择的阵列单元中的逻辑内容的输出数字信号。

9. 发明申请

US20050232024A1 Method for reading a memory array with neighbor effect cancellation 有权
标题翻译：读取具有相邻效果消除的存储器阵列的方法
公开(公告)号：US20050232024A1
公开(公告)日：2005-10-20
申请号：US10826375
申请日：2004-04-19
申请人： Shahar Atir , Oleg Dadashev , Yair Sofer , Eduardo Maayan
发明人： Shahar Atir , Oleg Dadashev , Yair Sofer , Eduardo Maayan
IPC分类号： G11C7/02 , G11C7/06 , G11C7/08 , G11C16/04 , G11C16/26
CPC分类号： G11C7/02 , G11C7/06 , G11C7/08 , G11C16/0475 , G11C16/0491 , G11C16/26
摘要： There is provided in accordance with embodiments of the present invention a method of reducing the neighbor effect in reading data in a non-volatile memory array by sensing adjacent memory cells in a virtual ground array of memory cells comprising sensing substantially simultaneously a state of adjacent memory cells, wherein a bit stored in a charge trapping region of each cell of the adjacent memory cells is in an identical state.
摘要翻译：根据本发明的实施例提供了一种通过感测存储器单元的虚拟接地阵列中的相邻存储器单元来减少在非易失性存储器阵列中读取数据中的相邻效应的方法，包括基本同时感测相邻存储器的状态单元，其中存储在相邻存储器单元的每个单元的电荷捕获区域中的位处于相同状态。

10. 发明授权

US07187595B2 Replenishment for internal voltage 有权
标题翻译：补充内部电压
公开(公告)号：US07187595B2
公开(公告)日：2007-03-06
申请号：US10862404
申请日：2004-06-08
申请人： Yair Sofer , Ori Elyada , Yoram Betser
发明人： Yair Sofer , Ori Elyada , Yoram Betser
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C16/12
摘要： A replenish circuit for a semiconductor memory device, including a bias current generating unit adapted to generate a bias current, a frequency controllable oscillator adapted to receive the bias current and to provide an oscillating output, and a pulse generator adapted to receive the oscillating output and to generate first and second pulses as a function of the oscillating output, the second pulse being embedded in the first pulse, the first pulse causing the bias current generating unit to be connected to a power supply, and the second pulse being fed to sample-and-hold circuitry adapted to sample the bias current and hold the value thereof during the first pulse.
摘要翻译：一种用于半导体存储器件的补充电路，包括适于产生偏置电流的偏置电流产生单元，适于接收偏置电流并提供振荡输出的频率可控振荡器和适于接收振荡输出的脉冲发生器，产生作为振荡输出的函数的第一和第二脉冲，第二脉冲被嵌入在第一脉冲中，第一脉冲使偏置电流产生单元连接到电源，并且第二脉冲被馈送到采样 - 并且保持电路适于在第一脉冲期间对偏置电流进行采样并保持其值。

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