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1. 发明授权

US08098525B2 Pre-charge sensing scheme for non-volatile memory (NVM) 有权
标题翻译：用于非易失性存储器（NVM）的预充电感测方案
公开(公告)号：US08098525B2
公开(公告)日：2012-01-17
申请号：US12232437
申请日：2008-09-17
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

2. 发明申请

US20120063238A1 PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM) 有权
标题翻译：非易失性存储器（NVM）的预充电传感方案
公开(公告)号：US20120063238A1
公开(公告)日：2012-03-15
申请号：US13301826
申请日：2011-11-22
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

3. 发明授权

US08593881B2 Pre-charge sensing scheme for non-volatile memory (NVM) 有权
标题翻译：用于非易失性存储器（NVM）的预充电感测方案
公开(公告)号：US08593881B2
公开(公告)日：2013-11-26
申请号：US13301826
申请日：2011-11-22
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

4. 发明申请

US20090073774A1 Pre-charge sensing scheme for non-volatile memory (NVM) 有权
标题翻译：用于非易失性存储器（NVM）的预充电感测方案
公开(公告)号：US20090073774A1
公开(公告)日：2009-03-19
申请号：US12232437
申请日：2008-09-17
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。可以根据每个地址的预定义表来选择预充电的全局位线。可以根据在下一个读取周期期间这些全局位线是否会干扰管道来完成全局位线的选择。

5. 发明授权

US07864588B2 Minimizing read disturb in an array flash cell 有权
标题翻译：最小化阵列闪存单元中的读取干扰
公开(公告)号：US07864588B2
公开(公告)日：2011-01-04
申请号：US12232418
申请日：2008-09-17
申请人： Yoram Betser , Yair Sofer , Oren Shlomo , Avri Harush
发明人： Yoram Betser , Yair Sofer , Oren Shlomo , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28 , G11C16/3427
摘要： A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.
摘要翻译：一种通过使用第一漏极电压来读取阵列单元并使用第二较低漏极电压来读取参考单元的方法来减小NVM单元中的读取干扰。阵列和参考单元的全局位线（GBL）上的漏极电压可能彼此基本相同，以保持主路径电容匹配，而参考单元的局部位线（LBL）上的漏极电压可能低于漏极本地位线上的电压（LBL）用于阵列单元以减少第二位效应。可以使用夹紧装置或降压装置来降低其排出口处的参考单元的漏极电压。

6. 发明申请

US20090073760A1 Minimizing read disturb in an array flash cell 有权
标题翻译：最小化阵列闪存单元中的读取干扰
公开(公告)号：US20090073760A1
公开(公告)日：2009-03-19
申请号：US12232418
申请日：2008-09-17
申请人： Yoram Betser , Yair Sofer , Oren Shlomo , Avri Harush
发明人： Yoram Betser , Yair Sofer , Oren Shlomo , Avri Harush
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28 , G11C16/3427
摘要： A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.
摘要翻译：一种通过使用第一漏极电压来读取阵列单元并使用第二较低漏极电压来读取参考单元的方法来减小NVM单元中的读取干扰。阵列和参考单元的全局位线（GBL）上的漏极电压可能彼此基本相同，以保持主路径电容匹配，而参考单元的局部位线（LBL）上的漏极电压可能低于漏极本地位线上的电压（LBL）用于阵列单元以减少第二位效应。可以使用夹紧装置或降压装置来降低其排出口处的参考单元的漏极电压。

7. 发明授权

US07532529B2 Apparatus and methods for multi-level sensing in a memory array 有权
标题翻译：用于存储器阵列中多级感测的装置和方法
公开(公告)号：US07532529B2
公开(公告)日：2009-05-12
申请号：US11464253
申请日：2006-08-14
申请人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
发明人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C16/32 , G11C2211/5634
摘要： A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.
摘要翻译：一种用于感测从存储器阵列内的阵列单元接收的信号的方法，所述方法包括以下步骤：产生与所述存储器阵列的所选阵列单元的电流成比例的模拟电压Vddr，以及将所述模拟电压Vddr与参考模拟电压Vcomp以产生输出数字信号。还提供了一种用于通过将来自存储器单元的信号变换为时间延迟来感测存储单元的方法，以及通过将时间延迟与参考单元的时间延迟进行比较来感测存储单元。还公开了相关装置。

8. 发明申请

US20060285402A1 APPARATUS AND METHODS FOR MULTI-LEVEL SENSING IN A MEMORY ARRAY 有权
标题翻译：用于存储阵列中多级感测的装置和方法
公开(公告)号：US20060285402A1
公开(公告)日：2006-12-21
申请号：US11464253
申请日：2006-08-14
申请人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
发明人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
IPC分类号： G11C5/14
CPC分类号： G11C11/5642 , G11C16/32 , G11C2211/5634
摘要： A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.
摘要翻译：一种用于感测从存储器阵列内的阵列单元接收的信号的方法，所述方法包括以下步骤：产生与所述存储器阵列的所选阵列单元的电流成比例的模拟电压Vddr，以及将所述模拟电压Vddr与参考模拟电压Vcomp以产生输出数字信号。还提供了一种用于通过将来自存储器单元的信号变换为时间延迟来感测存储单元的方法，以及通过将时间延迟与参考单元的时间延迟进行比较来感测存储单元。还公开了相关装置。

9. 发明授权

US07605579B2 Measuring and controlling current consumption and output current of charge pumps 有权
标题翻译：测量和控制电荷泵的电流消耗和输出电流
公开(公告)号：US07605579B2
公开(公告)日：2009-10-20
申请号：US11602222
申请日：2006-11-21
申请人： Yoram Betser , Alexander Kushnarenko , Oleg Dadashev
发明人： Yoram Betser , Alexander Kushnarenko , Oleg Dadashev
IPC分类号： G01R19/00 , G01R29/00 , G05F1/10
CPC分类号： H02M3/073 , H02M2001/0009
摘要： The present invention is a method and apparatus for regulating current consumption and output current of a charge pump. According to some embodiments of the present invention, a first current coming into the charge pump and a second current coming into a driver of at least one of one or more stages of the charge pump is measured. A control loop may regulate one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages.
摘要翻译：本发明是用于调节电荷泵的电流消耗和输出电流的方法和装置。根据本发明的一些实施例，测量进入电荷泵的第一电流和进入电荷泵的一个或多个级中的至少一个的驱动器的第二电流。控制回路可以调节电荷泵的一个或多个参数和/或连接到电荷泵的负载，例如通过调节以下的一个或多个：电源电压; 舞台的电压; 舞台的频率和/或占空比; 和阶段数。

10. 发明申请

US20080094127A1 Measuring and controlling current consumption and output current of charge pumps 有权
标题翻译：测量和控制电荷泵的电流消耗和输出电流
公开(公告)号：US20080094127A1
公开(公告)日：2008-04-24
申请号：US11602222
申请日：2006-11-21
申请人： Yoram Betser , Alexander Kushnarenko , Oleg Dadashev
发明人： Yoram Betser , Alexander Kushnarenko , Oleg Dadashev
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2001/0009
摘要： Measuring and controlling current consumption and output current of a charge pump by measuring a first current coming into the charge pump; and measuring a second current coming into a driver for at least one of the one or more stages of the charge pump. A control loop may one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages, or by decreasing the current consumption by adjusting a load connected to the output of the charge pump pipe. The first and second currents may be compared with first and second reference currents. A load connected to the charge pump may comprise non-volatile memory cells, and the charge pump may be implemented on a same integrated circuit chip as the memory cells.
摘要翻译：通过测量进入电荷泵的第一电流来测量和控制电荷泵的电流消耗和输出电流; 以及测量进入所述电荷泵的所述一个或多个阶段中的至少一个的驱动器的第二电流。控制回路可以是电荷泵的一个或多个参数和/或连接到电荷泵的负载，例如通过调节以下的一个或多个：电源电压; 舞台的电压; 舞台的频率和/或占空比; 或通过调节连接到电荷泵管的输出的负载来减小电流消耗。可以将第一和第二电流与第一和第二参考电流进行比较。连接到电荷泵的负载可以包括非易失性存储器单元，并且电荷泵可以在与存储器单元相同的集成电路芯片上实现。

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