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1. 发明申请

US20050232024A1 Method for reading a memory array with neighbor effect cancellation 有权
标题翻译：读取具有相邻效果消除的存储器阵列的方法
公开(公告)号：US20050232024A1
公开(公告)日：2005-10-20
申请号：US10826375
申请日：2004-04-19
申请人： Shahar Atir , Oleg Dadashev , Yair Sofer , Eduardo Maayan
发明人： Shahar Atir , Oleg Dadashev , Yair Sofer , Eduardo Maayan
IPC分类号： G11C7/02 , G11C7/06 , G11C7/08 , G11C16/04 , G11C16/26
CPC分类号： G11C7/02 , G11C7/06 , G11C7/08 , G11C16/0475 , G11C16/0491 , G11C16/26
摘要： There is provided in accordance with embodiments of the present invention a method of reducing the neighbor effect in reading data in a non-volatile memory array by sensing adjacent memory cells in a virtual ground array of memory cells comprising sensing substantially simultaneously a state of adjacent memory cells, wherein a bit stored in a charge trapping region of each cell of the adjacent memory cells is in an identical state.
摘要翻译：根据本发明的实施例提供了一种通过感测存储器单元的虚拟接地阵列中的相邻存储器单元来减少在非易失性存储器阵列中读取数据中的相邻效应的方法，包括基本同时感测相邻存储器的状态单元，其中存储在相邻存储器单元的每个单元的电荷捕获区域中的位处于相同状态。

2. 发明授权

US06836443B2 Apparatus and method of high speed current sensing for low voltage operation 失效
标题翻译：用于低电压工作的高速电流检测装置和方法
公开(公告)号：US06836443B2
公开(公告)日：2004-12-28
申请号：US10341933
申请日：2003-01-14
申请人： Oleg Dadashev
发明人： Oleg Dadashev
IPC分类号： G11C702
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/14 , G11C2207/063 , G11C2207/2227
摘要： A sensing system for a memory cell in a memory array includes a current integrator circuit configured to integrate a read current through the memory cell and a reference current through a reference memory cell. The integration process creates a set of differential measurement voltages that can be used to determine the state of the memory cell. By integrating the read current to obtain a measurement voltage, rather than directly comparing the read current to a reference current, the sensing system can use lower supply voltages than conventional sensing systems. In addition, because the measurement voltages are generated by integrating the read current over time, sensing operations are less sensitive to supply voltage fluctuations and the accuracy. Also, for memory cells that exhibit small read currents, the accuracy of sensing operations can be increased by increasing the period of integration.
摘要翻译：用于存储器阵列中的存储单元的感测系统包括电流积分器电路，其被配置为将通过存储器单元的读取电流与通过参考存储单元的参考电流进行积分。积分过程创建一组可用于确定存储单元状态的差分测量电压。通过集成读取电流以获得测量电压，而不是直接将读取电流与参考电流进行比较，感测系统可以使用比常规感测系统更低的电源电压。此外，由于通过对随时间的读取电流进行积分而产生测量电压，因此感测操作对电源电压波动和精度较不敏感。此外，对于显示小读取电流的存储单元，可以通过增加积分周期来增加感测操作的精度。

3. 发明申请

US20090073774A1 Pre-charge sensing scheme for non-volatile memory (NVM) 有权
标题翻译：用于非易失性存储器（NVM）的预充电感测方案
公开(公告)号：US20090073774A1
公开(公告)日：2009-03-19
申请号：US12232437
申请日：2008-09-17
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。可以根据每个地址的预定义表来选择预充电的全局位线。可以根据在下一个读取周期期间这些全局位线是否会干扰管道来完成全局位线的选择。

4. 发明授权

US07202654B1 Diode stack high voltage regulator 有权
标题翻译：二极管堆高压稳压器
公开(公告)号：US07202654B1
公开(公告)日：2007-04-10
申请号：US11236359
申请日：2005-09-27
申请人： Oleg Dadashev , Alexander Kushnarenko
发明人： Oleg Dadashev , Alexander Kushnarenko
IPC分类号： G05F3/16
CPC分类号： G05F3/262
摘要： A high voltage regulator including a current mirror including a pair of transistors, one of the transistors being connected to a node that outputs an output voltage Vout, a diode stack that includes a plurality of serially connected transistors T0, T1, T2, . . . Tn, wherein the transistor T1 is connected to a node n0, to which is connected another transistor T0 that receives an input bias voltage Vbias, and wherein a feedback voltage fb from node n0 is fed to an input of the differential amplifier, the differential amplifier receiving an input reference voltage Vref at one of its other inputs, and is also connected to positive voltage supply Vdd, the differential amplifier outputting to an NMOS transistor M, and wherein the high voltage regulator has a large diode stack gain and lower GDA*GNMOS*m, resulting in a generally constant feedback (loop) gain Gloop, wherein the loop gain is given by: Loop Gain=Gloop=Gstack*GDA*GNMOS*m wherein m is the ratio of the two currents I1 and I2, that is, I2=mI1, Gstack is the gain of the diode stack, GDA is the gain of the differential amplifier and GNMOS is the gain of the NMOS transistor M.
摘要翻译：一种高电压调节器，包括包括一对晶体管的电流镜，其中一个晶体管连接到输出输出电压V OUT的节点;二极管叠层，包括多个串联连接的晶体管T T 1，T 2，...，N 2，。。其中晶体管T 1连接到与另一个晶体管T 0连接的节点n 0 0 < SUB>接收输入偏置电压V SUB偏置，并且其中来自节点n0的反馈电压fb被馈送到差分放大器的输入端，差分放大器接收输入参考电压V SUB参考电压，并且还连接到正电压源Vdd，该差分放大器输出到NMOS晶体管M，并且其中高压调节器具有大的二极管叠层增益和更低的G N N N * N，导致大体上恒定的反馈（环路）增益G ，其中环路增益为给了

5. 发明申请

US20070069711A1 DIODE STACK HIGH VOLTAGE REGULATOR 有权
标题翻译：二极管堆高电压稳压器
公开(公告)号：US20070069711A1
公开(公告)日：2007-03-29
申请号：US11236359
申请日：2005-09-27
申请人： Oleg Dadashev , Alexander Kushnarenko
发明人： Oleg Dadashev , Alexander Kushnarenko
IPC分类号： G05F3/16
CPC分类号： G05F3/262
摘要： A high voltage regulator including a current mirror including a pair of transistors, one of the transistors being connected to a node that outputs an output voltage Vout, a diode stack that includes a plurality of serially connected transistors T0, T1, T2, . . . Tn, wherein the transistor T1 is connected to a node n0, to which is connected another transistor T0 that receives an input bias voltage Vbias, and wherein a feedback voltage fb from node n0 is fed to an input of the differential amplifier, the differential amplifier receiving an input reference voltage Vref at one of its other inputs, and is also connected to positive voltage supply Vdd, the differential amplifier outputting to an NMOS transistor M, and wherein the high voltage regulator has a large diode stack gain and lower GDA*GNMOS*m, resulting in a generally constant feedback (loop) gain Gloop wherein the loop gain is given by: Loop Gain=Gloop=Gstack*GDA*GNMOS*m wherein m is the ratio of the two currents I1 and I2, that is, I2=mI1, Gstack is the gain of the diode stack, GDA is the gain of the differential amplifier and GNMOS is the gain of the NMOS transistor M.
摘要翻译：一种高电压调节器，包括包括一对晶体管的电流镜，其中一个晶体管连接到输出输出电压V OUT的节点;二极管叠层，包括多个串联连接的晶体管T T 1，T 2，...，N 2，。。其中晶体管T 1连接到与另一个晶体管T 0连接的节点n 0 0 < SUB>接收输入偏置电压V SUB偏置，并且其中来自节点n0的反馈电压fb被馈送到差分放大器的输入端，差分放大器接收输入参考电压V SUB参考电压，并且还连接到正电压源Vdd，该差分放大器输出到NMOS晶体管M，并且其中高压调节器具有大的二极管叠层增益和较低的G N N N N N * M，导致通常恒定的反馈（环路）增益G 其中给出了环路增益通过：<？in-line-formula description =“In-line Formulas”end =“lead”？> Loop Gain = G = G 其中m是两个电流I的比值，其中m是两个电流I的比值＆lt; 1＆gt;和＆lt; 2＆gt;，即I 2＆gt; = m 1＆lt; 1＆lt;＆lt; >是二极管堆叠的增益，G 是差分放大器的增益，并且G NMOS NMOS是NMOS晶体管M的增益。

6. 发明申请

US20060285402A1 APPARATUS AND METHODS FOR MULTI-LEVEL SENSING IN A MEMORY ARRAY 有权
标题翻译：用于存储阵列中多级感测的装置和方法
公开(公告)号：US20060285402A1
公开(公告)日：2006-12-21
申请号：US11464253
申请日：2006-08-14
申请人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
发明人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
IPC分类号： G11C5/14
CPC分类号： G11C11/5642 , G11C16/32 , G11C2211/5634
摘要： A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.
摘要翻译：一种用于感测从存储器阵列内的阵列单元接收的信号的方法，所述方法包括以下步骤：产生与所述存储器阵列的所选阵列单元的电流成比例的模拟电压Vddr，以及将所述模拟电压Vddr与参考模拟电压Vcomp以产生输出数字信号。还提供了一种用于通过将来自存储器单元的信号变换为时间延迟来感测存储单元的方法，以及通过将时间延迟与参考单元的时间延迟进行比较来感测存储单元。还公开了相关装置。

7. 发明授权

US06081456A Bit line control circuit for a memory array using 2-bit non-volatile memory cells 有权
标题翻译：使用2位非易失性存储单元的存储器阵列的位线控制电路
公开(公告)号：US06081456A
公开(公告)日：2000-06-27
申请号：US243976
申请日：1999-02-04
申请人： Oleg Dadashev
发明人： Oleg Dadashev
IPC分类号： G11C7/10 , G11C7/12 , G11C7/18 , G11C11/56 , G11C16/04 , G11C16/24 , H01L27/115 , G11C16/06
CPC分类号： G11C7/1072 , G11C11/5671 , G11C16/0475 , G11C16/24 , G11C7/12 , G11C7/18 , H01L27/115
摘要： A bit line control circuit for accessing an array of 2-bit non-volatile memory cells. Each memory cell has a first and a second charge trapping regions. A set of bit lines extends between the array and the bit line control circuit. The bit line control circuit includes pass transistors that selectively route pairs of bit lines to corresponding voltage control circuits in either a first order or a second (reversed) order. This enables both the first and second charge trapping regions of the memory cells to be accessed from the same voltage control circuits. In one embodiment, the bit line control circuit includes a first-level pass transistor coupled to each bit line. A second set of bit lines is coupled to the first-level pass transistors. A parallel-connected pair of second-level pass transistors is coupled to each bit line in the second set of bit lines. A third set of bit lines is coupled to the second-level pass transistors. The voltage control circuits are coupled to the third set of bit lines. The voltage control circuits apply voltages to the third set of bit lines to perform read, write and erase operations in the memory cells of the memory array. The first and second level pass transistors provide a consistent path for accessing all memory cells in the array, as well as handling the edge conditions introduced by the right-most and left-most columns of memory cells.
摘要翻译：一种用于访问2位非易失性存储单元阵列的位线控制电路。每个存储单元具有第一和第二电荷俘获区域。一组位线在阵列和位线控制电路之间延伸。位线控制电路包括通过晶体管，其以第一或第二（反向）顺序选择性地将位线对对应到相应的电压控制电路。这使得能够从相同的电压控制电路访问存储器单元的第一和第二电荷捕获区域。在一个实施例中，位线控制电路包括耦合到每个位线的第一级传输晶体管。第二组位线耦合到第一级传输晶体管。并联的第二级通过晶体管对耦合到第二组位线中的每个位线。第三组位线耦合到第二级传输晶体管。电压控制电路耦合到第三组位线。电压控制电路将电压施加到第三组位线，以在存储器阵列的存储单元中执行读取，写入和擦除操作。第一级和第二级传输晶体管提供用于访问阵列中的所有存储器单元的一致路径，以及处理由最右边和最左边的存储单元列引入的边缘条件。

8. 发明申请

US20160246315A1 BANDGAP REFERENCE CIRCUIT WITH LOW OUTPUT IMPEDANCE STAGE AND POWER-ON DETECTOR 有权
标题翻译：具有低输出阻抗级和上电检测器的带宽参考电路
公开(公告)号：US20160246315A1
公开(公告)日：2016-08-25
申请号：US14129525
申请日：2013-09-09
申请人： Joseph SHOR , George L. GEANNOPOULOS , Fabrice PAILLET , Lan D. VU , Oleg DADASHEV
发明人： Joseph SHOR , George L. GEANNOPOULOS , Fabrice PAILLET , Lan D. VU , Oleg DADASHEV
IPC分类号： G05F1/46 , G05F1/59 , G06F1/26 , G05F1/575
CPC分类号： G05F1/468 , G05F1/575 , G05F1/59 , G05F3/30 , G06F1/26
摘要： Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.
摘要翻译：描述了一种装置，其包括：带隙芯，用于提供控制信号; 以及耦合到带隙磁芯的输出级，输出级接收控制信号并在输出节点处提供低阻抗输出。

9. 发明申请

US20120063238A1 PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM) 有权
标题翻译：非易失性存储器（NVM）的预充电传感方案
公开(公告)号：US20120063238A1
公开(公告)日：2012-03-15
申请号：US13301826
申请日：2011-11-22
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译：管道效应可以显着降低闪存性能。公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。专用的读取顺序使感测节点面向预先充电的管道的部分。该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。根据每个地址的预定义表格选择预充电的全局位线。根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

10. 发明授权

US07532529B2 Apparatus and methods for multi-level sensing in a memory array 有权
标题翻译：用于存储器阵列中多级感测的装置和方法
公开(公告)号：US07532529B2
公开(公告)日：2009-05-12
申请号：US11464253
申请日：2006-08-14
申请人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
发明人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C16/32 , G11C2211/5634
摘要： A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.
摘要翻译：一种用于感测从存储器阵列内的阵列单元接收的信号的方法，所述方法包括以下步骤：产生与所述存储器阵列的所选阵列单元的电流成比例的模拟电压Vddr，以及将所述模拟电压Vddr与参考模拟电压Vcomp以产生输出数字信号。还提供了一种用于通过将来自存储器单元的信号变换为时间延迟来感测存储单元的方法，以及通过将时间延迟与参考单元的时间延迟进行比较来感测存储单元。还公开了相关装置。

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