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1. 发明授权

US07172938B2 Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US07172938B2
公开(公告)日：2007-02-06
申请号：US10987340
申请日：2004-11-12
申请人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim , Jae-Hwang Kim
发明人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim , Jae-Hwang Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.
摘要翻译：隧道电介质层，电荷俘获层，第一长度限定层和第二长度限定层依次沉积在半导体衬底上。这些层依次构图。通过选择性侧蚀刻凹入第一长度限定层第一图案的两个侧壁。在形成用于覆盖曝光的电荷俘获层的阻挡层和用于填充凹陷部分的栅极层之后，对栅极层进行图案化以形成间隔物形栅极。用于源区和漏区的掺杂区形成在与栅极相邻的半导体衬底上。

2. 发明申请

US20050106816A1 Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20050106816A1
公开(公告)日：2005-05-19
申请号：US10987340
申请日：2004-11-12
申请人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim , Jae-Hwang Kim
发明人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim , Jae-Hwang Kim
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.
摘要翻译：隧道电介质层，电荷俘获层，第一长度限定层和第二长度限定层依次沉积在半导体衬底上。这些层依次构图。通过选择性侧蚀刻凹入第一长度限定层第一图案的两个侧壁。在形成用于覆盖曝光的电荷俘获层的阻挡层和用于填充凹陷部分的栅极层之后，对栅极层进行图案化以形成间隔物形栅极。用于源区和漏区的掺杂区形成在与栅极相邻的半导体衬底上。

3. 发明申请

US20070111451A1 Flash memory device and method of manufacturing the same 审中-公开
标题翻译：闪存装置及其制造方法
公开(公告)号：US20070111451A1
公开(公告)日：2007-05-17
申请号：US11650237
申请日：2007-01-05
申请人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
发明人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42328
摘要： A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.
摘要翻译：提供一种包括隧道介电层，浮栅，层间电介质层和形成在半导体衬底上的至少两个模层的闪存器件及其制造方法。通过顺序地图案化这些层，形成彼此对准的第一模具层图案和浮动栅极层图案。选择性地横向蚀刻第一模具层图案的侧表面的暴露部分，从而在其侧壁中形成具有凹槽的第一模具层第二图案。栅极电介质层形成在与浮动栅层图案相邻的半导体衬底上。具有由第二模层图案中的凹槽确定的宽度的控制栅极形成在栅介质层上。通过去除第一模具层第二图案，在控制门的侧壁上形成间隔物。使用间隔物作为蚀刻掩模来选择性地蚀刻层间电介质层和浮栅层图案的暴露部分，以形成具有由沟槽和间隔物的宽度限定的宽度的浮动栅极。

4. 发明授权

US07192833B2 Flash memory device and method of manufacturing the same 有权
公开(公告)号：US07192833B2
公开(公告)日：2007-03-20
申请号：US11025279
申请日：2004-12-29
申请人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
发明人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328
摘要： A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

5. 发明申请

US20050153502A1 Flash memory device and method of manufacturing the same 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US20050153502A1
公开(公告)日：2005-07-14
申请号：US11025279
申请日：2004-12-29
申请人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
发明人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328
摘要： A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.
摘要翻译：提供一种包括隧道介电层，浮栅，层间电介质层和形成在半导体衬底上的至少两个模层的闪存器件及其制造方法。通过顺序地图案化这些层，形成彼此对准的第一模具层图案和浮动栅极层图案。选择性地横向蚀刻第一模具层图案的侧表面的暴露部分，从而在其侧壁中形成具有凹槽的第一模具层第二图案。栅极电介质层形成在与浮动栅层图案相邻的半导体衬底上。具有由第二模层图案中的凹槽确定的宽度的控制栅极形成在栅介质层上。通过去除第一模具层第二图案，在控制门的侧壁上形成间隔物。使用间隔物作为蚀刻掩模来选择性地蚀刻层间电介质层和浮栅层图案的暴露部分，以形成具有由沟槽和间隔物的宽度限定的宽度的浮动栅极。

6. 发明授权

US07432159B2 Electrically erasable programmable read-only memory (EEPROM) device and methods of fabricating the same 失效
标题翻译：电可擦除可编程只读存储器（EEPROM）器件及其制造方法
公开(公告)号：US07432159B2
公开(公告)日：2008-10-07
申请号：US11242209
申请日：2005-10-03
申请人： Jae-Hwang Kim , Seung-Beom Yoon , Kwang-Wook Koh , Chang-Hun Lee , Sung-Ho Kim , Sung-Chul Park , Ju-Ri Kim
发明人： Jae-Hwang Kim , Seung-Beom Yoon , Kwang-Wook Koh , Chang-Hun Lee , Sung-Ho Kim , Sung-Chul Park , Ju-Ri Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.
摘要翻译： EEPROM器件包括设置在半导体衬底的预定区域以限定有源区的器件隔离层，与器件隔离层交叉的一对控制栅极和有源区，插入控制栅极之间的一对选择栅极，器件隔离层和有源区以及顺序地堆叠在控制栅极和有源区之间的浮置栅极和隔间栅极电介质图案。EEPROM器件还包括插入浮置栅极和有源区域之间的存储晶体管的栅极绝缘层，以及隧道绝缘层比存储晶体管的栅极绝缘层薄，并且选择晶体管的栅极绝缘层插入在选择栅极和有源区之间。隧道绝缘层在与浮动栅极相邻的一侧对准。

7. 发明申请

US20060079045A1 Electrically erasable programmable read-only memory (EEPROM) device and methods of fabricating the same 失效
公开(公告)号：US20060079045A1
公开(公告)日：2006-04-13
申请号：US11242209
申请日：2005-10-03
申请人： Jae-Hwang Kim , Seung-Beom Yoon , Kwang-Wook Koh , Chang-Hun Lee , Sung-Ho Kim , Sung-Chul Park , Ju-Ri Kim
发明人： Jae-Hwang Kim , Seung-Beom Yoon , Kwang-Wook Koh , Chang-Hun Lee , Sung-Ho Kim , Sung-Chul Park , Ju-Ri Kim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

8. 发明授权

US07589376B2 Electrically erasable programmable read-only memory (EEPROM) device and methods of fabricating the same 失效
标题翻译：电可擦除可编程只读存储器（EEPROM）器件及其制造方法
公开(公告)号：US07589376B2
公开(公告)日：2009-09-15
申请号：US12199307
申请日：2008-08-27
申请人： Jae-Hwang Kim , Seung-Beom Yoon , Kwang-Wook Koh , Chang-Hun Lee , Sung-Ho Kim , Sung-Chul Park , Ju-Ri Kim
发明人： Jae-Hwang Kim , Seung-Beom Yoon , Kwang-Wook Koh , Chang-Hun Lee , Sung-Ho Kim , Sung-Chul Park , Ju-Ri Kim
IPC分类号： H01L29/94
CPC分类号： H01L27/11521 , H01L27/115
摘要： An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.
摘要翻译： EEPROM器件包括设置在半导体衬底的预定区域以限定有源区的器件隔离层，与器件隔离层交叉的一对控制栅极和有源区，插入控制栅极之间的一对选择栅极，器件隔离层和有源区以及顺序地堆叠在控制栅极和有源区之间的浮置栅极和隔间栅极电介质图案。EEPROM器件还包括插入浮置栅极和有源区域之间的存储晶体管的栅极绝缘层，以及隧道绝缘层比存储晶体管的栅极绝缘层薄，并且选择晶体管的栅极绝缘层插入在选择栅极和有源区之间。隧道绝缘层在与浮动栅极相邻的一侧对准。

9. 发明授权

US07015541B2 Memory cell including stacked gate sidewall patterns and method for fabricating same 有权
标题翻译：包括堆叠栅极侧壁图案的存储单元及其制造方法
公开(公告)号：US07015541B2
公开(公告)日：2006-03-21
申请号：US10758523
申请日：2004-01-14
申请人： Jae-Hwang Kim , Hee-Seog Jeon
发明人： Jae-Hwang Kim , Hee-Seog Jeon
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/66833 , H01L29/7923
摘要： A memory cell and a method for fabricating same. The memory cell comprises a source region and a drain region formed in a semiconductor substrate and a channel region defined between the source and drain regions. Charge storage layers are formed the channel region. A gate insulating layer is formed on the channel region between the charge storage layers, and a gate electrode is formed on the gate insulating layer and the charge trapping storage layers.
摘要翻译：一种存储单元及其制造方法。存储单元包括形成在半导体衬底中的源极区域和漏极区域以及限定在源极和漏极区域之间的沟道区域。电荷存储层形成沟道区。在电荷存储层之间的沟道区域上形成栅极绝缘层，并且在栅极绝缘层和电荷俘获存储层上形成栅电极。

10. 发明授权

US08187167B2 Monitoring apparatus for laparoscopic surgery and display method thereof 有权
标题翻译：腹腔镜手术监护仪及其显示方法
公开(公告)号：US08187167B2
公开(公告)日：2012-05-29
申请号：US11660934
申请日：2005-10-18
申请人： Jae-Hwang Kim
发明人： Jae-Hwang Kim
IPC分类号： A61B1/00 , A61B1/04
CPC分类号： A61B1/00045 , A61B1/3132
摘要： A monitor apparatus for a laparoscopic surgery rotates images captured by a laparoscope as an endoscope and displayed on monitors for the laparoscopic surgery clockwise or counter-clockwise according to commands for rotating the images by surgeons who use image rotation manipulation parts such that the images of surgical devices displayed on the monitors are arranged in the direction where the surgeons can actually manipulate the laparoscopic surgical devices most conveniently.
摘要翻译：用于腹腔镜手术的监视器装置将作为内窥镜的腹腔镜拍摄的图像旋转，根据用于使用图像旋转操作部件的外科医生旋转图像的命令，将腹腔镜手术顺时针或逆时针方向显示在监视器上，以便外科手术显示在显示器上的装置沿着外科医生最方便地实际操作腹腔镜手术装置的方向排列。

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